Abstract: Low VOC, dielectric compositions suitable for use in circuit board manufacture are disclosed. Also disclosed are methods of making circuit boards using the low VOC, dielectric compositions.

Abstract: A trench isolation method of a semiconductor integrated circuit is provided. In the trench isolation method, a mask pattern which defines a first opening and a second opening wider than the first opening is formed on a semiconductor substrate. A first spacer for filling the first opening and a second spacer are formed at the sidewalls of the second opening. A sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate is formed in the second opening surrounded by the second spacer. The semiconductor substrate under the first and second spacers is exposed by selectively removing the first and second spacers. A deep trench region and a shallow trench region are formed in the exposed semiconductor substrate and under the sacrificial material layer, respectively, by etching the exposed semiconductor substrate and the sacrificial material layer pattern. An isolation layer filling the deep trench region and the shallow trench region is formed.

Abstract: A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of each of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.

Abstract: A photolithographic apparatus for rapidly processing semiconductor wafers. In the photolithographic apparatus, a plurality of steppers are in parallel connected to one coater/developer. The steppers are in parallel connected to one coater/developers, where the steppers process the semiconductor wafer at a low speed and the coater/developers process the semiconductor wafer at a high speed, to thereby remove a bottleneck phenomenon. Therefore, the photolithographic apparatus according to the present invention may rapidly perform a photolithography process.

Abstract: The invention provides a method of forming a conductive structure on an integrated circuit substrate. A metal bump, of a first material, is structured on the substrate so that the metal bump electrically contacts a metal part on the substrate. A protective layer is formed on the metal bump. The first material has a first conductivity. The protective layer is of a second material which has a second conductivity which is more than the first conductivity.

Abstract: A method of using dielectric anti-reflective coating (DARC) in conjunction with bottom anti-reflective coating (BARC) to form an anti-reflective barrier layer is provided. The anti-reflective layer conforms to the topography of the substrate surface and is adapted to function effectively in both annealed and unannealed states. The method of using DARC in combination with BARC also inhibits the nitride layer of a gate stack to seep into adjacent photoresist layers and adversely affect the composition of the photoresist.

Abstract: The invention relates to a system and a method for manufacturing semiconductor devices on a wafer with the steps of: coating (201) a photoresist onto said wafer, heating (202) said wafer to a prebake temperature for outgassing the solvent of the photoresist, exposing (203) said wafer to deep UV light for chemically modifying said photoresist in predetermined areas, heating (204) said wafer to a post exposure bake temperature for activating a chemical reaction, developing (205) said photoresist, stabilizing (206) said photoresist, meteorology inspection (207), etching, wet processing or implanting ion, wherein said stabilizing (206) of said photoresist occurs before the beginning of the etch process and comprises a controlled chemical contamination of said photoresist surface by ammonia/amine chemicals.

Abstract: The invention is a process for building-up printed wiring boards using metal foil coated with toughened benzocyclobutene-based dielectric polymers. The invention is also a toughened dielectric polymer comprising benzocyclobutene-based monomers or oligomers, ethylenically unsaturated polymer additive, and, optionally, a photoactive compound.

Abstract: An optical exposure method in photolithography applied for precise processing when semiconductor devices are produced. A pattern on a photomask is projected and exposed on a register on a base plate with an exposure device including a deformation illumination system, a photomask and a projection lens. The deformation illumination system is composed of a light source, a diaphragm and a condenser lens, and the diaphragm is provided with a linear through-hole. The optical exposure method uses a ray of linear light for illumination or two rays of linear light for illumination that are parallel with the pattern. The two rays of linear light are symmetrical with respect to an optical axis. These rays are parallel with the pattern in a position separate from the optical axis of the exposure device when the photomask pattern is a line and space pattern.

Abstract: An interdigital electrode of a SAW device is protected by a protective layer during a photo-lithography etching process which is used to apply a bonding pad. As the bonding pad can be formed by the photo-lithography etching process, it is possible to obtain regularly shaped bonding pads without damaging the characteristics of the SAW device.

Abstract: A process for making a two-component plasma-deposited photo-oxidizable organosilicon film on a substrate from a silicon donor and an organic precursor. Subjecting selected areas of the film to photo-oxidation allows selective etching of the non-photo-oxidized or photo-oxidized areas of the film. The process is used as a resist for patterning substrates in the fabrication of solid-state devices. It is of particular use in patterning heat sensitive substrates and accomplishing microlithography in a closed chamber process at other than atmospheric pressure. The process allows photo-oxidation with ultraviolet light at wavelengths closer to visible light than that for conventional photoresists. The processed film exhibits selective wetting properties between the non-photo-oxidized and photo-oxidized areas of the film.

Abstract: Fabrication of arbitrary profile micro-optical structures (lenses, gratings, etc.) and, if desired, with optomechanical alignment marks simultaneously during fabrication is based upon the use of low-contrast photosensitive material that, when exposed to a spatially variable energy dosage of electromagnetic radiation, can be processed to achieve multi-level or continuous surface-relief microstructures. By varying the exposure dose spatially based upon predetermined contrast curves of the photosensitive material, arbitrary one-dimensional (1-D) or two-dimensional (2-D) surface contours, including spherical, aspherical, toroidal, hyperbolic, parabolic, and ellipsoidal, can be achieved with surface sags greater than 15 &mgr;m. Surface profiles with advanced phase correction terms (e.g., Zernike polynomials) can be added to increase the alignment tolerance and overall system performance of the fabricated structure can also be fabricated.

Abstract: When a resist film is formed by discharging a resist solution onto the front face of a wafer housed in a cup, a relation between the film thickness of a resist film and the line width of a circuit pattern when the resist film is exposed into a predetermined pattern and thereafter developed is obtained in advance, from that relation, a line width with less variations corresponding to the changes in film thickness of the resist film is selected from among line widths within a designated region to form a resist film to have the film thickness corresponding to the selected line width. Accordingly, the line width of the circuit pattern after development is not likely to vary regardless of the changes in film thickness of the resist film formed on the wafer.

Abstract: A method of stripping a photoresist layer comprising applying a re-coating material on the photoresist layer which extends through and fills openings in a first layer on which the photoresist layer is disposed, ashing the stack comprised of the photoresist layer and the re-coating material, and removing such re-coating material as remains in the openings in the first layer after the ashing.

Abstract: The invention relates to a developer for photosensitive polyimide resin compositions, comprising an alkaline aqueous solution containing a basic compound (A) represented by a formula (1): wherein X+ is N+ or P+, R is an alkyl group having 1 to 20 carbon atoms or an aryl group having 6 to 10 ring forming carbon atoms, Y− is a monovalent anion, m is 0 or 1, n is 3 or 4, and m+n is 4, with the proviso that when m is 0, n is 4, and R is an alkyl group, the total number of carbon atoms of 4 alkyl groups is at least 13, or when m is 1, n is 3, and R is an alkyl group, the total number of carbon atoms of 3 alkyl groups is at least 6.

Abstract: A stepper device and method of using the stepper device in which a light source in the stepper generates an annular or multipole pattern of light having a relatively large coherency value that is used to expose inner fields of a photoresist-coated wafer. The light source generates an annular or multipole pattern of light having a relatively small coherency that is used to expose outer fields of the wafer adjacent its edge. The use of light having a relatively small coherence value to expose the outer fields of the wafer causes the exposure width of isolated features to be relatively large compared to the exposure width of dense features. As a result, after etching, the isolated features and the dense features can have the same width since etching is more effective for dense features.

Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

Abstract: The invention relates to an integrated electric circuit comprising a metal layer provided with a passivation layer. The passivation layer is made of a monomolecular film which is placed on the surface of the metal layer. The monomolecular film is formed prior to contacting the metal layer with metal wires. The wires are pushed through the passivation layer with a force strong enough to pierce the monomolecular film. In the alternative, the film may be selectively removed at defined locations in preparation for the contacting with the wires.

Abstract: A semiconductor device achieving higher integration without deterioration of electrical characteristics thereof, a method of manufacturing the semiconductor device, and a method of forming a resist pattern used for that can be obtained. According to the method of forming a resist pattern used for the method of manufacturing a semiconductor device, light is directed via a mask onto a resist film surface formed on a substrate to project a first optical image having a width equal to or less than the wavelength of the light onto the resist surface. The mask is shifted relative to the substrate. Via the shifted mask, light is directed onto the resist film surface to project a second optical image having a width equal to or less than the wavelength of the light onto the resist surface such that the second optical image partially overlaps faith a region where the first optical image is projected.

Abstract: A method of producing a micro structure on a substrate which has a support portion and a plate-like portion supported thereby at a distance from the substrate, comprising the steps of forming a spacer layer consisting of an insulating material on a substrate having an electrically conductive layer formed on its surface, forming a latent image layer consisting of an electrically conductive material on the spacer layer at a site where the plate-like portion of an intended structure is to be formed, producing an aperture, where a part of the electrically conductive layer is exposed, on the spacer layer at a site where the supporting portion of an intended structure is to be formed, forming a structure layer consisting of plating film inside of the aperture and on the latent image layer by electroplating the electrically conductive layer as a cathode, and removing the spacer layer.