Patents Examined by Nicole Barreca
  • Patent number: 6492096
    Abstract: A patterned molecular self-assembly is provided. The patterned molecular self-assembly comprises a support having an exposed patterned surface and a non-patterned surface. A compound is selectively adsorbed on the exposed patterned surface. The compound may comprise a first compound selectively adsorbed on the exposed patterned surface and a second compound selectively adsorbed on the first compound to form at least one bilayer. The patterned molecular self-assembly may further comprise a first set of bilayers and a second set of bilayers wherein the first set of bilayers has a different composition than the second set of bilayers.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 10, 2002
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Yanjing Liu, Guy A. Schick
  • Patent number: 6489083
    Abstract: A process for forming a masking database that includes defining a first feature level for the masking database corresponding to a first layer. The first feature level includes a first region with a first feature density and a second region with a second feature density that is substantially different from the first feature density. The process also includes defining a second feature level for the masking database corresponding to a second layer, wherein the second feature level is to be formed over a substrate after the first feature level has been formed over or within the substrate. A first feature within the second feature level will be formed within the first region, a second feature within the second feature level will be formed within the second region. The second layer will have a first thickness over the first layer within the first region and has a second thickness over the first layer within the second region.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: December 3, 2002
    Assignee: Motorola, Inc.
    Inventors: Bradley P. Smith, Edward O. Travis, Sejal N. Chheda, Ruiqi Tian
  • Patent number: 6489082
    Abstract: A negative pattern is formed to be transparent in the far ultraviolet region including the wavelength 193 nm of an ArF excimer laser and, despite its chemical structure having high dry etching, does not swell and has excellent resolution. An acid-catalyzed reaction is utilized wherein a &ggr;-hydroxy or &dgr;-hydroxy carboxylic acid structure is partially or entirely converted to a &ggr;-lactone or &dgr;-lactone structure. The negative pattern is developed with an aqueous alkali solution without swelling.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: December 3, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hattori, Yuko Tsuchiya, Hiroshi Shiraishi
  • Patent number: 6485895
    Abstract: A method for forming a fine pattern in a semiconductor substrate, comprises the steps of (a) coating a target layer to be etched on a semiconductor substrate with a resist composition comprising at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator, wherein the free radical initiator is one which is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound, wherein said coating step results in forming a resist compound layer comprising the resist composition; (b) performing a lithography process on the resist compound layer to form a photoresist pattern of at least one opening having a first width, wherein the target layer is exposed through the first width; and (c) heating the resist compound layer having the photoresist pattern formed therein to a temperature equal to or higher than the glass transition temperature of the at least one compound, an
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: November 26, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Yool Kang, Joo-tae Moon, Jeong-hee Chung, Sang-gyun Woo
  • Patent number: 6485891
    Abstract: A production method of a semiconductor device, includes the steps of emitting an excimer laser from a light source, illuminating a pattern on a mask with the excimer laser emitted from the light source and passed through a filter, exposing a resist on a substrate of the semiconductor with the excimer laser passed through the mask, and forming a pattern on the substrate in accordance with a portion of the resist exposed with the excimer laser.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: November 26, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Minori Noguchi, Yukio Kenbo, Yoshitada Oshida, Masataka Shiba, Yasuhiro Yoshitaka, Makoto Murayama
  • Patent number: 6472128
    Abstract: Antihalation compositions and methods for reducing the reflection of exposure radiation of a photoresist overcoated said compositions. The antihalation compositions of the invention comprise a resin binder and material capable of causing a thermally induced crosslinking reaction of the resin binder.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: October 29, 2002
    Assignee: Shipley Company, L.L.C.
    Inventors: James W. Thackeray, George W. Orsula
  • Patent number: 6472124
    Abstract: A fabrication method for a self-aligned metal-insulator-metal capacitor is described. A plurality of metal interconnects is provided. A metal interconnect is etched back to form a recess in the metal interconnect using a patterned photoresist as a mask. A capacitor insulator is formed on the resulting structure, partially filling the recess in the metal interconnect and covering other metal interconnects. A top electrode metal layer is then deposited on the capacitor insulator, completely filling the recess in the metal interconnect. The top electrode metal layer that is formed above the recess of the metal interconnect is subsequently removed.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: October 29, 2002
    Assignee: Macronix International Co., Ltd.
    Inventor: Henry Chung
  • Patent number: 6465159
    Abstract: A robust method for etching an organic low-k insulating layer on a semiconductor device, as disclosed herein, includes introducing into a processing chamber a substrate with an organic insulating layer and an overlying mask layer having an aperture. A plasma is then developed within the chamber from an oxidizing gas and a passivation gas. The passivation gas is preferably either a silicon containing gas or a boron containing gas, or both. The ratio of the oxidizing gas to the passivation gas is preferably at least 10:1. In addition, an inert carrier gas may be provided. The plasma is then used to etch the organic insulating layer through the mask layer, thereby forming a via having essentially vertical sidewalls in the organic low-k insulating layer.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: October 15, 2002
    Assignee: Lam Research Corporation
    Inventors: Tuqiang Ni, Nancy Tran
  • Patent number: 6465161
    Abstract: In a process for manufacturing integrated circuit elements or the like by photolithography, a method for reducing detrimental influence on resist shape due to properties of a substrate or acidity of substrate surface in case where a chemically amplified resist or the like is used as a photoresist, and a substrate-treating agent composition to be used for this method are described. The substrate-treating agent composition comprises a solution containing a salt between at least one basic compound selected from among primary, secondary and tertiary amines and nitrogen-containing heterocyclic compounds and an organic acid such as a sulfonic acid or a carboxylic acid. This composition is coated on a substrate surface having thereon a bottom anti-reflective coating such as SiON layer, baked and, if necessary washed, then a chemically amplified resist is coated on the thus-treated substrate, exposed and developed to form a resist pattern on the substrate.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: October 15, 2002
    Assignee: Clariant Finance (BVI) Limited
    Inventors: Wen-Bing Kang, Shoko Matsuo, Ken Kimura, Yoshinori Nishiwaki, Hatsuyuki Tanaka
  • Patent number: 6461800
    Abstract: A resist patterning method allows further fine patterning of semiconductor integrated circuits. First, a resist is formed on an underlying layer (1). The resist is selectively exposed, whereby an exposed portion and an unexposed portion are formed. Then, development processing of the resist is performed using a developing solution. In the development process, the resist in the exposed portion is removed at a first velocity and then the resist in the unexposed portion is removed at a second velocity lower than the first velocity, to thereby form a resist pattern (2).
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: October 8, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kouichirou Tsujita
  • Patent number: 6458513
    Abstract: A micro machined structure includes one or more temporary bridges for temporarily coupling the micro machined structure to a support structure.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: October 1, 2002
    Assignee: Input/Output, Inc.
    Inventors: Lianzhong Yu, Howard D. Goldberg, Duli Yu
  • Patent number: 6456358
    Abstract: The present invention provides a surface-treatment apparatus for forming a plurality of photoresist-isolating walls on an organic electroluminescent panel. The surface-treatment apparatus has a photoresist-coating module, a prebaking unit, an exposure unit, a post-exposure surface treatment module with an alkaline atmosphere, a development module and a hard baking unit. The photoresist-coating module coats a photoresist layer on the surface of the organic electroluminescent panel. The prebaking unit bakes the photoresist layer on the organic electroluminescent panel by a heating plate and initially drives solvents from the photoresist layer. The exposure unit performs an UV exposure process on the photoresist layer after the prebaking. The post-exposure surface treatment module with an alkaline atmosphere bakes the photoresist layer by a heating plate after the exposure process, wherein the alkaline atmosphere surfacely terminates a self-catalyzed reaction of photo-acid ions of the photoresist layer.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: September 24, 2002
    Assignee: Ritek Display Technology Co.
    Inventor: Tien-Rong Lu
  • Patent number: 6451511
    Abstract: Multiple exposure of a photoresist layer having an exposure depth depending upon the amount of exposure energy applied are executed at different respective exposure energy amounts through a plurality of respective photomasks with different respective opening patterns. The photoresist layer is then processed for image reversal.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: September 17, 2002
    Assignee: TDK Corporation
    Inventor: Yuji Asanuma
  • Patent number: 6444401
    Abstract: A method of forming a field emission device for a flat panel display includes operating a projection exposure apparatus. This comprises placing three layers of exposure sensitive material on a device in succession, with steps of exposure and removal of material between deposition of subsequent layers of exposure sensitive material. Furthermore, a field emission device is formed by exposing a third layer of exposure sensitive material, wherein a tip on the field emission device or plurality of tips on the field emission devices can be obtained with differing sharpness characteristics by varying the depth and diameter of holes in a mask used during exposure of exposure sensitive material.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: September 3, 2002
    Assignee: Winbond Electronics Corporation
    Inventor: Szetsen Steven Lee
  • Patent number: 6444408
    Abstract: Polymerizable monomers having silicon containing groups that are transparent at 193 nm; and ethylenically unsaturated group are provided. Polymers from these monomers can be used in processes for forming sub-100 nm images with a chemically amplified, radiation sensitive bilayer resist. The bilayer resist is disposed on a substrate and comprises (i) a top imaging layer comprising a radiation sensitive acid generator and (ii) an organic underlayer. The bilayer resist can be used in the manufacturing of integrated circuits.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Phillip Joe Brock, Richard Anthony DiPietro, Donald Clifford Hofer, Ratnam Sooriyakumaran, Gregory Michael Wallraff
  • Patent number: 6444403
    Abstract: A method of making a multilayer buildup printed circuit board and mounting substrate wherein a resin laminated wiring sheet, which has a copper foil, an epoxy-acrylate photosensitive resin composition having a fluorene structure, and a conductive pattern, are overlaid on the conductive pattern side of a supporting substrate at 100° C. and 3 kg/cm2, and adhered thereto at 200 to 300° C. and 10 kg/cm2. The copper foil is entirely etched by wet-etching or is etched into a predetermined pattern so as to form a wiring structure. Since the epoxy-acrylate photosensitive resin composition is not treated at 100° C. or more, and hence is in a semi-cured state, the epoxy-acrylate photosensitive resin composition can be heat-bonded onto the supporting substrate.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: September 3, 2002
    Assignees: NEC Corporation, Nippon Steel Chemical Co., Ltd.
    Inventors: Tadanori Shimoto, Koji Matsui, Takero Teramoto, Hironobu Kawasato
  • Patent number: 6444398
    Abstract: A lithographic mask (FIG. 9 or FIG. 10) that is primarily used for SCALPEL processing has a substrate (100). Layers (102, 104, 106, 108, 110, and 112) are formed and selectively patterned and etched to form E-beam exposure windows (118) and skirt regions (120) framing the windows (118). The skirt regions (120) and some portions of the patterned features (124) within the window (118) are formed having thicker/thinner regions of material or formed of different material whereby different regions of the mask (FIG. 9) scatter energy to differing degrees. The different scattering regions on the mask allow SCALPEL patterns to be formed on the wafer with improved critical dimension (CD) control, reduced aberrant feature formation, and improved yield.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: September 3, 2002
    Assignee: Motorola, Inc.
    Inventor: Kevin David Cummings
  • Patent number: 6440647
    Abstract: A process for removing patterned negative working resist from the surface of a substrate during manufacture of printed wiring boards is disclosed. The process includes the steps of contacting the patterned resist with a stripping solution containing an alkalinity source as well as a source of ammonium ions. The stripping solution is characterized in that it does not contain volatile organic compounds (VOCs).
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: August 27, 2002
    Assignee: Alpha Metals, Inc.
    Inventor: Eric Yakobson
  • Patent number: 6440645
    Abstract: A process for the production of a device having a surface microstructure of wells or channels. In the process one or more steps of screen-printing the microstructure as a curable material onto a plastic substrate, and curing the material. Such a device is also obtained by applying onto a substrate a material that is polymerizable or depolymerizable by irradiation, applying a negative or positive resist photoresist respectively, irradiating the structure and removing the unpolymerized or depolymerized material.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: August 27, 2002
    Assignee: Cambridge Sensors Limited
    Inventors: Bernadette Yon-Hin, James McCann, Saji Eapen, Christopher Robin Lowe
  • Patent number: 6440641
    Abstract: The present invention provides a method for controlling the mechanical stresses at the interfaces of the metal and dielectric materials in the printed wiring substrates of high density interconnects. The invention enables the minimization of cracking due to these stresses and does so in an economically attractive process that is able to meet the needs of today's high density interconnect applications. In one embodiment, the method of the present invention dispenses mechanical stresses in a high density interconnect printed wiring board substrate having a first patterned conductive layer formed over an upper surface of the substrate. The patterned conductive layer includes multiple conductive lines each having edges that define the boundaries of the conductive lines. The method of the invention forms a composite dielectric layer over the first patterned conductive layer and between the edges of the conductive layer.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 27, 2002
    Assignee: Kulicke & Soffa Holdings, Inc.
    Inventors: James L. Lykins, Jan I. Strandberg