Patents Examined by Nikolay K Yushin
  • Patent number: 10896805
    Abstract: A method for electron beam lithography. The method may comprise fabricating a multi-layer mask and interposing the multi-layer mask between an electron beam and an energy-sensitive layer to thereby expose the energy-sensitive layer to the electron beam through the mask. Fabricating the multi-layer mask may comprises providing a first mask layer fabricated from a first mask material (e.g. silicon nitride) which defines one or more feature apertures corresponding to features of interest and coating an electron-energy-reducing material (e.g. gold) onto the first mask layer to thereby provide a second mask layer.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 19, 2021
    Inventor: Gary William Leach
  • Patent number: 10896868
    Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90, a first terminal that projects outward from the sealing part 90 and a connector 51 that has a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75, and a proximal end part 45 connected to the first terminal via a conductor layer 75. The head part 40 has a single first projection part 41 that projects toward the electronic element 95. The first projection part 41 sinks into the conductive adhesive 75 and comes into point contact with the front surface of the electronic element 95. The proximal end part 45 has a plurality of protrusion parts 49 or a support surface 46, contacting the conductor layer 70.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: January 19, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Yuji Morinaga
  • Patent number: 10892191
    Abstract: A method of manufacturing a semiconductor device, includes irradiating a division region of a semiconductor wafer with laser to form a plurality of modified portions arranged in a direction along the division region in the semiconductor wafer, and splitting the semiconductor wafer into a plurality of semiconductor chips using a groove generated from the plurality of modified portions in the semiconductor wafer. The plurality of modified portions is at a first interval in a first part of the division region and at a second interval smaller than the first interval in a second part of the division region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu Ono, Yusuke Dohmae
  • Patent number: 10892443
    Abstract: Provided is a display device. The display device includes a flexible display panel configured to display an image, and a window disposed on a display surface of the flexible display panel. The window includes a first protection layer, a thin film glass layer disposed on the first protection layer, and a second protective layer disposed on the thin film glass layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hung Kun Ahn, Youngsang Park, Sungguk An
  • Patent number: 10892162
    Abstract: There is provided a method of forming a silicon film, which includes: a film forming step of forming the silicon film on a base, the silicon film having a film thickness thicker than a desired film thickness; and an etching step of reducing the film thickness of the silicon film by supplying an etching gas containing bromine or iodine to the silicon film.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 12, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuhiro Okada, Tatsuya Miyahara, Keisuke Fujita
  • Patent number: 10886141
    Abstract: Provided is a method of depositing tungsten, in which depositing a tungsten nucleation layer is formed by performing a unit cycle at least once, wherein the unit cycle includes an absorption step in which a first process gas is provided on a substrate such that at least a portion of the first process gas is absorbed on the substrate, a first purge step in which a purge gas is provided on the substrate to purge the first process gas which has not been absorbed on the substrate, a reaction step in which a gas containing tungsten is provided on the substrate as a second process gas to form a unit deposition film on the substrate, a second purge step in which a purge gas is provided on the substrate to purge a reaction by-product on the substrate, a processing step in which a processing gas containing a hydrogen (H) element is provided on the substrate to reduce the concentration of an impurity in the unit deposition film, and a third purge step in which a purge gas is provided on the substrate to purge the proce
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 5, 2021
    Assignee: WONIK IPS CO., LTD.
    Inventor: Won Jun Yoon
  • Patent number: 10886499
    Abstract: A light emitting display apparatus includes a passivation layer on a thin film transistor, a light emitting diode on the passivation layer, the light emitting diode having an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, and a hydrogen absorbing layer on the light emitting diode, the hydrogen absorbing layer including an inorganic material having a mass percentage of 0.08% to 50%.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Goeun Kim, YoungHoon Shin
  • Patent number: 10879289
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
  • Patent number: 10879069
    Abstract: A hard mask film forming method includes preparing a substrate in which an etching target film is formed on a base. The hard mask film forming method further includes forming a hard mask film on the substrate while controlling film forming parameters such that tensile stress is set as initial film stress and the tensile stress monotonously increases from a bottom surface of the hard mask film toward an upper surface of the hard mask film.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yutaka Fujino
  • Patent number: 10875143
    Abstract: An apparatus for CMP includes a platen, a wafer carrier retaining a semiconductor wafer during a polishing operation, a dresser configured to recondition a polishing pad disposed on the platen during the polishing operation, and a vibration-monitoring system configured to detect vibrations during the polishing operation. The vibration-monitoring system includes a first vibration sensor configured to generate a plurality of first vibration signals. An end point is triggered to the polishing when a change between the plurality of vibration signals reaches a value.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: James Jeng-Jyi Hwang, Jiann Lih Wu, He Hui Peng, Chi-Ming Yang
  • Patent number: 10879052
    Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen Liao
  • Patent number: 10872967
    Abstract: A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 22, 2020
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Yi-Chun Shih, Shun-Min Yeh
  • Patent number: 10872829
    Abstract: A thin film transistor, a display substrate and a method for repairing the same, and a display device are provided. The thin film transistor includes: an active region, a gate insulating layer disposed on a side of the active region, and a gate disposed on a side of the gate insulating layer distal to the active region, and the active region includes a first electrode contact region at one end of the active region, a second electrode contact region at the other end of the active region, and a plurality of connection regions between the first electrode contact region and the second electrode contact region, and each of the plurality of connection regions is coupled to the first electrode contact region and the second electrode contact region, and every two adjacent connection regions are provided with an opening therebetween and are spaced apart from each other by the opening.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 22, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haitao Wang, Guangyao Li, Jun Wang, Qinghe Wang, Ning Liu, Dongfang Wang
  • Patent number: 10868039
    Abstract: A manufacturing method of a semiconductor device is provided. The method includes forming a sacrificial layer with different material layers, and etching the sacrificial layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Byung Woo Kang
  • Patent number: 10859878
    Abstract: According to one embodiment, a display device comprises a first substrate, a second substrate opposed to the first substrate and including a first organic film, a first convex portion extending in a first direction, a second convex portion extending in a second direction intersecting the first direction, and a third convex portion aligned with the first convex portion in the second direction and extending in the first direction, and a sealing member located in a second area around a first area in which an image is displayed, wherein the first convex portion, the second convex portion and the third convex portion are located between the first organic film and the sealing member.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 8, 2020
    Assignee: JAPAN DISPLAY INC.
    Inventors: Tomokazu Ishikawa, Masaru Nakakomi
  • Patent number: 10861978
    Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Su Lee, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang, Dae Ho Kim, Jae Neung Kim, Myoung Geun Cha, Sang Gab Kim, Yu-Gwang Jeong
  • Patent number: 10861694
    Abstract: A method of manufacturing an insulation layer on silicon carbide includes first preparing a surface of the silicon carbide, then forming a first part of the insulation layer on the surface at a temperature lower than 400° Celsius. Finally, a second part of the insulation layer is formed by depositing a dielectric film on the first part. The surface of the silicon carbide is illuminated by a light at a wavelength below and/or equal to 450 nm during and/or after the formation of the first part of the insulation layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 8, 2020
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Yuji Komatsu
  • Patent number: 10854638
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
  • Patent number: 10854734
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 1, 2020
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Yi-Chun Shih, Shun-Min Yeh
  • Patent number: 10854815
    Abstract: An apparatus for manufacturing a display apparatus includes: a chamber; a plurality of source units outside the chamber, wherein the plurality of source units which accommodate a deposition material and transform the deposition material into gas; a nozzle unit in the chamber, wherein the nozzle unit is connected to the plurality of source units and injects, into the chamber, the deposition material supplied from one of the plurality of source units; and a regulating unit between each of the plurality of source units and the nozzle unit, wherein the regulating unit interrupts the deposition material supplied from each of the plurality of source units to the nozzle unit and selectively connects the plurality of source units with the nozzle unit.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangjin Han, Junha Park, Eugene Kang, Dongwook Kim, Cheollae Roh, Jaewan Seol, Seongho Jeong, Myungsoo Huh, Mingyu Seo