Abstract: Disclosed is a display apparatus including a first thin film transistor (TFT) and a second thin film transistor having a bottom gate structure and including an oxide semiconductor layer. The first TFT may be used as a switching device and the second TFT may be used as a driving device, and these TFTs have different operation properties from each other. One or more embodiments of the present disclosure provides a method of arranging a plurality of TFTs having different properties in a display apparatus. This not only provides a display apparatus with TFTs integrated at a high density but also an efficient way of driving the display apparatus.

Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.

Abstract: A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.

Abstract: A sensor including a layer of amorphous selenium (a-Se) and at least one charge blocking layer is formed by depositing the charge blocking layer over a substrate prior to depositing the amorphous selenium, enabling the charge blocking layer to be formed at elevated temperatures. Such a process is not limited by the crystallization temperature of a-Se, resulting in the formation of an efficient charge blocking layer, which enables improved signal amplification of the resulting device. The sensor can be fabricated by forming first and second amorphous selenium layers over separate substrates, and then fusing the a-Se layers at a relatively low temperature.

Abstract: A display device may include: a substrate including a display area and a non-display area; and pixels provided on the display area, and each including sub-pixels each including an emission area and a non-emission area. Each sub-pixel may include a pixel circuit layer including at least one transistor, and a display element layer including at least one light emitting element configured to emit light and connected to the transistor. The display element layer may include: a first electrode and a second electrode spaced apart from each other with the light emitting element interposed therebetween; the light emitting element connected between the first and second electrodes; and a planarization layer provided on the pixel circuit layer, and coming into contact with at least a portion of each of opposite ends of the light emitting element. The planarization layer may overlap with each of the first electrode and the second electrode.

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

Abstract: A semiconductor device includes a substrate having a first side and a second side opposite to the first side; a first optical element at the first side of the substrate; and a semiconductor stack on the substrate. The semiconductor stack includes a first reflective structure; a second reflective structure; a cavity region between the first reflective structure and the second reflective structure and having a first surface and a second surface opposite to the first surface; and a confinement layer in one of the second reflective structure and the first reflective structure. The semiconductor device further includes a first electrode and a second electrode on the first surface.

Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.

Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method of forming an LED involves forming a semiconductor structure on a substrate. The semiconductor structure includes a p-side semiconductor layer, an n-side semiconductor layer, and an active light emitting layer between the p-side semiconductor layer and the n-side semiconductor layer. The semiconductor structure is also formed to include a light outcoupling surface facing the substrate. The light outcoupling surface has a diameter less than twice an electron diffusion length of a material of the semiconductor structure. The method further involves implanting ions in an outer region of the semiconductor structure, then annealing the outer region after the ions have been implanted. The annealing causes the ions to intermix with atoms within the outer region, thereby increasing a bandgap of the outer region.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device can include a trench formed in a first dielectric layer, a trench filler layer that fills a portion of the trench, a conductive layer over the trench filler layer, and a second dielectric layer over the conductive layer. The second dielectric layer is disposed in the trench. The semiconductor device can also include a contact structure configured to connect to the conductive layer through a hole in the second dielectric layer.

Abstract: A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.

Abstract: Provided are a method for etching and growing a semiconductor substrate in the same device system, and a device therefor. The method for manufacturing a semiconductor substrate includes a first heating step of heating a heat treatment space which contains a semiconductor substrate and a transmission/reception body that transports atoms between the semiconductor substrate and the transmission/reception body such that a temperature gradient is formed between the semiconductor substrate and the transmission/reception body, and a second heating step of heating the same with the temperature gradient being vertically inverted.

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate at least including a pixel area and a hole area; a plurality of sub-pixels arranged on the base substrate and located in the pixel area; a hole in the hole area; a first barrier dam arranged between the sub-pixels and the hole and at least partially surrounding the hole; an organic material layer including at least one film layer, wherein an orthographic projection of the organic material layer on the base substrate falls within the pixel area; and a filling structure, wherein at least a portion of the filling structure is arranged between the hole and the first barrier dam, and the filling structure and the at least one film layer of the organic material layer are located in the same layer and include the same material.

Abstract: Described herein is a technique capable of improving characteristics of a film. According to one or more embodiments of the present disclosure, there is provided a technique that includes: (a) performing (a-1) supplying in parallel a metal-containing gas and a reducing gas that contains silicon and hydrogen and is free of halogen to a substrate in a process chamber, and (a-2) exhausting an inner atmosphere of the process chamber; (b) repeatedly performing (a) a first number of times; (c) supplying a nitrogen-containing gas to the substrate in the process chamber and exhausting the inner atmosphere of the process chamber after performing (b); and (d) repeatedly performing (a) a second number of times.

Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate and a first recess. The first recess sequentially extends through a second dielectric layer, a third insulating layer, a first dielectric layer, a second insulating layer, a first insulating layer, an active layer, and a portion of a barrier layer. A bottom surface of the first recess is formed inside the barrier layer.

Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

Abstract: An electronic device includes: a capacitor; an insulating layer; at feast one trench provided in the insulating layer; and a first conductive plug, at least part of which is surrounded by the insulating layer. The capacitor includes: a first lower electrode provided along an inner wall of the at least one trench, a dielectric layer provided on the first lower electrode, and an upper electrode provided on the dielectric layer. At least part of the first conductive plug is positioned between an upper surface of the insulating layer and a lowermost portion of the at least one trench.