Patents Examined by Nikolay K Yushin
  • Patent number: 11230668
    Abstract: The present invention provides an etchant less causing damage to IGZOs. The etchant of the present invention comprises hydroxyethanediphosphonic acid (A), one or more phosphonic acids (B), hydrogen peroxide (C), nitric acid (D), a fluorine compound (E), an azole (F), and an alkali (G), and is characterized in that the phosphoric acids (B) comprise one or more phosphonic acids selected from the group consisting of diethylenetriaminepentamethylenephosphonic acid, N,N,N?,N?-ethylenediaminetetrakismethylenephosphonic acid, and aminotrimethylenephosphonic acid and that the proportion of the hydroxyethanediphosphonic acid (A) is in the range of 0.01-0.1 mass % and the proportion of the phosphonic acids (B) is in the range of 0.003-0.04 mass %.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 25, 2022
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Youzou Yamada, Toshiyuki Goto
  • Patent number: 11233074
    Abstract: The present application provides an array substrate and a manufacturing method thereof. The array substrate includes a thin film transistor and a storage capacitor prepared on a substrate; the thin film transistor includes a gate, an active layer, and a source/drain; the storage capacitor includes a first electrode and a second electrode isolated therefrom by a dielectric layer; the gate is disposed above the first electrode and located at one end of the first electrode; and the second electrode corresponds to a portion of the first electrode non-corresponding to the gate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 25, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Zhenguo Lin, Xingyu Zhou, Yuanjun Hsu, Poyen Lu
  • Patent number: 11227875
    Abstract: A display device includes a pixel connected to a scan line, and a data line crossing the scan line, wherein the pixel includes a light-emitting element, a driving transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line, and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal that is applied to the scan line. The driving transistor includes a first active layer including an oxide semiconductor, and a first oxide layer disposed on the first active layer and including an oxide semiconductor. The first switching transistor includes a second active layer including an oxide semiconductor, and the first oxide layer is not disposed on the second active layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 18, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myoung Hwa Kim, Joon Seok Park, So Young Koo, Tae Sang Kim, Yeon Keon Moon, Geun Chul Park, Jun Hyung Lim, Kyung Jin Jeon
  • Patent number: 11227995
    Abstract: A ReRAM device manufactured using 2-D Si2Te3 (silicon telluride) nanowires or nanoplates. The Si2Te3 nanowires exhibit a unique reversible resistance switching behavior driven by an applied electrical potential, which leads to switching of the NWs from a high-resistance state (HRS) to a low-resistance state (LRS). This switched LRS is highly stable unless the opposite potential is applied to switch the resistance back. This provides a new class of resistive switching based on semiconductor rather than dielectric materials. In several embodiments, the polarity of the initially applied potential along the Si2Te3 nanowires defines the switch “on” and “off” directions, which become permanent once set.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: January 18, 2022
    Inventors: Jingbiao Cui, Keyue Wu, Jiyang Chen, Xiao Shen
  • Patent number: 11217698
    Abstract: A thin film transistor is provided. The thin film transistor includes an active layer, and the active layer includes a plurality of stacked structures, and each of the stacked structures includes: a N-layer indium oxidation layer; a gallium oxidation layer, the gallium oxidation layer is provided on the indium oxidation layer of the N-layer indium oxidation layer; and a zinc oxidation layer is provided on the gallium oxidation layer. These stacked structures improve the performance of the thin film transistor. A preparation method of the thin film transistor and a display panel containing the thin film transistor is also provided.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: January 4, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chuanbao Luo
  • Patent number: 11217610
    Abstract: An active matrix substrate includes: a first substrate; and first electrodes, a dielectric layer covering the first electrodes, and a first water-repelling layer in this sequence on the first substrate, wherein the dielectric layer has a multilayer structure including two or more layers and includes a silicon nitride film and a metal-oxide film between the silicon nitride film and the first water-repelling layer, and the silicon nitride film has an oxygen-containing surface layer region on a surface thereof that is in contact with the metal-oxide film.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 4, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Atsushi Hachiya, Hiroaki Furukawa, Kazuya Tsujino
  • Patent number: 11205664
    Abstract: A highly reliable semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a first conductor and a second conductor over the second oxide, a third insulator over the first conductor, a fourth insulator over the second conductor, a third oxide over the second oxide, a fifth insulator over the third oxide, a third conductor that is positioned over the fifth insulator and overlaps with the third oxide, a sixth insulator covering the first to fifth insulators, the first oxide, the second oxide, and the first to third conductors, and a seventh insulator over the sixth insulator.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 21, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryota Hodo, Tomoyo Kamogawa, Katsuaki Tochibayashi
  • Patent number: 11205667
    Abstract: Disclosed is a method of preparing a thin film transistor substrate, a thin film transistor substrate, and a display apparatus. The method includes forming a conductive material layer, forming a hydrophobic insulation layer on the conductive material layer, forming a photoresist layer on the hydrophobic insulation layer, patterning the photoresist layer to form a photoresist pattern, removing a segment in the hydrophobic insulation layer that is not covered by the photoresist pattern to form a hydrophobic insulation pattern, and removing a segment in the conductive material layer that is not covered by the hydrophobic insulation pattern to form a conductive pattern.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 21, 2021
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY, CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kui Gong, Dezhi Xu, Wei Tian, Honggang Gu, Yuhu Zhang
  • Patent number: 11205673
    Abstract: An image sensor includes a plurality of pixel sensing portions arranged in m columns and n rows. Each of the pixel sensing portions includes at least one thin film transistor and a photodetection diode (13) including n-type (16), intrinsic (15) and p-type (14) semiconductor layers. The p-type semiconductor layer (14) includes a multi-layered structure including lower (142) and upper (141) p-type semiconductor layered portions. The upper p-type semiconductor layered portion (141) has a band gap greater than 1.7 eV and has a p-type dopant in an amount not less than two times of that of the lower p-type semiconductor layered portion (142). An image sensing-enabled display apparatus and a method of making the image sensor are also disclosed.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 21, 2021
    Assignee: SHANGHAI HARVEST INTELLIGENCE TECHNOLOGY CO., LTD.
    Inventors: Hong-Yih Tseng, Jiandong Huang
  • Patent number: 11201179
    Abstract: Embodiments of the present disclosure provide a thin film transistor assembly, an array substrate and a display panel. The thin film transistor assembly includes a first thin film transistor and a second thin film transistor disposed on a substrate. The first thin film transistor includes a first source electrode, a first drain electrode, and a first active layer. The second thin film transistor includes a second source electrode. The first source electrode is disposed on a side of the first active layer facing towards the substrate. The first drain electrode is disposed on a side of the first active layer facing away from the substrate. An orthogonal projection of the first source electrode on the substrate overlaps an orthogonal projection of the second source electrode on the substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 14, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanwei Ren, Wulijibaier Tang, Xiaoguang Li, Jingyi Xu, Yuelin Wang, Lei Jia, Yanan Yu, Guolei Zhi
  • Patent number: 11195861
    Abstract: A display device and a method of manufacturing the same. The display device includes a pixel connected to a scan line and a data line intersecting the scan line, and a driving transistor and a switching transistor disposed in the pixel. The driving transistor includes a substrate, a first active layer disposed on the substrate, a first gate electrode disposed on the first active layer, and a second insulating film contacting the first gate electrode and the first gate electrode. The switching transistor includes a second active layer disposed on the substrate, a second gate electrode disposed on the second active layer, a first insulating film contacting the second active layer and the second gate electrode, and a second insulating film covering the first insulating film. The first insulating film and the second insulating film are made of different materials from each other.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Geun Chul Park, Joon Seok Park, Tae Sang Kim, Yeon Keon Moon, Jun Hyung Lim, Kyung Jin Jeon
  • Patent number: 11195885
    Abstract: A display device includes: a first substrate; a second substrate on the first substrate; a pixel between the first substrate and the second substrate and including a pixel area and a non-pixel area around the pixel area; a color filter between the pixel and the second substrate and overlapping with the pixel area; and a plurality of protrusions between the second substrate and the color filter, and each of the protrusions has a width that decreases as a distance from the second substrate increases.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 7, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gak Seok Lee, Byung-Chul Kim, Inok Kim, Jaemin Seong, Inseok Song, Keunchan Oh, Jieun Jang, Chang-Soon Jang, Sun-Kyu Joo
  • Patent number: 11189735
    Abstract: A semiconductor device includes a gate electrode, a semiconductor film, and a conductive film. The semiconductor film includes an oxide semiconductor material. The semiconductor film includes a channel region, a low-resistance region, and an intermediate region. The channel region is opposed to the gate electrode. The low-resistance region has a lower electric resistance than the channel region. The intermediate region is provided between the low-resistance region and the channel region. The conductive film is provided selectively in contact with the low-resistance region of the semiconductor film.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 30, 2021
    Assignee: JOLED INC.
    Inventors: Hiroshi Hayashi, Naoki Asano, Ryo Koshiishi
  • Patent number: 11189604
    Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chao-Kai Hung, Chien-Wei Chang, Ya-Chen Shih, Hung-Jung Tu, Hung-Yi Lin, Cheng-Yuan Kung
  • Patent number: 11189734
    Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 30, 2021
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Yuichiro Hanyu, Hiroki Hidaka
  • Patent number: 11177388
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 16, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Patent number: 11177296
    Abstract: An array substrate, a display device, a thin film transistor, and a method for manufacturing an array substrate are disclosed. The array substrate includes a base substrate, an active layer, and a cover layer. The active layer is on the base substrate, the cover layer is on a side, away from the base substrate, of the active layer and covers the array substrate, the cover layer includes a metal conductive portion and a transparent insulating metal oxide portion, the metal conductive portion and the transparent insulating metal oxide portion include an identical metal element, and the metal conductive portion is electrically connected to the active layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 16, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventor: Ning Liu
  • Patent number: 11177281
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 16, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Patent number: 11177356
    Abstract: The present application discloses a thin film transistor. The thin film transistor includes a first source electrode and a first drain electrode spaced apart from each other; an active layer on the first source electrode and the first drain electrode, the active layer having a channel part between the first source electrode and the first drain electrode, a source electrode contact part in contact with the first source electrode, and a drain electrode contact part in contact with the first drain electrode; a second source electrode on a side of the source electrode contact part distal to the first source electrode, the second source electrode being electrically connected to the first source electrode; and a second drain electrode on a side of the drain electrode contact part distal to the first drain electrode, the second drain electrode being electrically connected to the first drain electrode.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 16, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Wei Liu
  • Patent number: 11171089
    Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin