Patents Examined by Nikolay K Yushin
  • Patent number: 11557678
    Abstract: A transistor includes a first gate electrode, a composite channel layer, a first gate dielectric layer, and source/drain contacts. The composite channel layer is over the first gate electrode and includes a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer stacked in sequential order. The first gate dielectric layer is located between the first gate electrode and the composite channel layer. The source/drain contacts are disposed on the composite channel layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Marcus Johannes Henricus Van Dal, Blandine Duriez, Georgios Vellianitis, Gerben Doornbos, Mauricio Manfrini
  • Patent number: 11557680
    Abstract: A thin film transistor, a method for manufacturing the same and a display apparatus comprising the same are disclosed, in which the thin film transistor comprises a semiconductor formed on a substrate, a gate insulating film formed on the semiconductor, a gate electrode formed on the gate insulating film, a first insulating film formed on the substrate, a first conductor portion formed on the first insulating film and formed at one side of the semiconductor, and a second conductor portion formed on the first insulating film and formed at another side of the semiconductor, wherein a first portion of the first insulating film may be formed between the semiconductor and the first conductor portion, and a second portion of the first insulating film may be formed between the semiconductor and the second conductor portion.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 17, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Jaeman Jang, JungSeok Seo, PilSang Yun, InTak Cho
  • Patent number: 11557679
    Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 17, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata
  • Patent number: 11552111
    Abstract: A semiconductor device having favorable and stable electrical characteristics is provided. The semiconductor device includes a first and a second transistor over an insulating surface. The first and the second transistors each include a first insulating layer, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a first conductive layer overlapping with the semiconductor layer with the second insulating layer interposed therebetween. The first insulating layer includes a convex first region that overlaps with the semiconductor layer and a second region that does not and is thinner than the first region. The first conductive layer includes a part over the second region where a lower surface of the first conductive layer is positioned below a lower surface of the semiconductor layer. The second transistor further includes a third conductive layer overlapping with the semiconductor layer with the first insulating layer interposed therebetween.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 10, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masami Jintyou, Yukinori Shima
  • Patent number: 11552112
    Abstract: The present disclosure provides a display device comprising: a first thin film transistor including a first semiconductor pattern disposed on a substrate and comprising poly-silicon, and a first gate electrode; a middle layer on the first gate electrode; a second thin film transistor including a second semiconductor pattern disposed on the middle layer and comprising an oxide semiconductor, and a second gate electrode; and a storage capacitor including first to fourth storage electrodes overlapping with each other.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 10, 2023
    Assignee: LG Display Co., Ltd.
    Inventor: Hyunsoo Lim
  • Patent number: 11545458
    Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
  • Patent number: 11545578
    Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasumasa Yamane, Takashi Hirose, Teruyuki Fujii, Hajime Kimura, Daigo Shimada
  • Patent number: 11543705
    Abstract: According to one embodiment, a display device comprises a first substrate, a second substrate opposed to the first substrate and including a first organic film, a first convex portion extending in a first direction, a second convex portion extending in a second direction intersecting the first direction, and a third convex portion aligned with the first convex portion in the second direction and extending in the first direction, and a sealing member located in a second area around a first area in which an image is displayed, wherein the first convex portion, the second convex portion and the third convex portion are located between the first organic film and the sealing member.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: January 3, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Tomokazu Ishikawa, Masaru Nakakomi
  • Patent number: 11545510
    Abstract: This disclosure discloses an array substrate, and a production method, a display panel, and a display apparatus thereof. Particularly, this disclosure proposes a method of producing an array substrate, having the following steps: providing a substrate having a drive transistor region and a switch transistor region thereon; forming an preset layer for active layer on a side of the substrate; patterning the preset layer for active layer to form a drive active layer and a switch active layer, wherein an orthographic projection of the drive active layer on the substrate is located in the drive transistor region, an orthographic projection of the switch active layer on the substrate is located in the switch transistor region, and a carrier concentration in the drive active layer is less than a carrier concentration in the switch active layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 3, 2023
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Wei Song, Ce Zhao, Yuankui Ding, Ming Wang, Yingbin Hu, Qinghe Wang, Wei Li, Liusong Ni
  • Patent number: 11545386
    Abstract: A workpiece unit that includes a workpiece, a tape stuck to the workpiece; and an annular frame to which an outer circumferential edge of the tape is stuck and which has an opening defined centrally therein. The workpiece is disposed in the opening in the annular frame and supported on the annular frame by the tape, and at least one of the tape and the annular frame has an irreversible discoloring section that discolors in response to an external stimulus. Such a configuration makes it possible to determine whether or not a process involving an external stimulus has been carried out on the workpiece unit, based on the appearance of the workpiece unit (i.e., based on whether the irreversible discoloring section has been discolored or not).
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 3, 2023
    Assignee: DISCO CORPORATION
    Inventors: Yoshinobu Saito, Masayuki Matsubara
  • Patent number: 11545551
    Abstract: A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinya Sasagawa, Erika Takahashi, Katsuaki Tochibayashi, Ryo Arasawa
  • Patent number: 11538961
    Abstract: A light-emitting diode is disclosed, which includes: a substrate; a light-emitting diode chip disposed on the substrate; and a quantum dot film disposed on the light-emitting diode chip, wherein the quantum dot film includes a plurality of quantum dots and a matrix material, and a plurality of particles are dispersed in the matrix material, wherein the plurality of particles are conductive particles, semiconductor particles, or a combination thereof.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 27, 2022
    Inventors: Chung-Hwa Lee, Jian-Ging Chen
  • Patent number: 11535934
    Abstract: A vaporizer includes a tank in which liquid material is heated to generate gas, a cabinet which houses the tank, and a conduit which supplies the gas to the outside of the cabinet. The vaporizer also includes a flow rate measuring means which measures a flow rate of the gas flowing through said conduit, and a heater plate which heats the conduit. The cabinet comprises a detachable panel that is a panel which can be removed. A first support member is fixed directly or indirectly to said cabinet at a position other than said detachable panel, the flow rate measuring means is supported by said first support member, and the heater plate is supported between said flow rate measuring means and said detachable panel by said first support member.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 27, 2022
    Assignee: Hitachi Metals, Ltd.
    Inventors: Akira Sasaki, Yoshinori Yoshida
  • Patent number: 11532650
    Abstract: A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. A display device includes a transistor and a capacitor. The transistor includes a first insulating layer, a first semiconductor layer in contact with the first insulating layer, a second insulating layer in contact with the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer via an opening portion provided in the second insulating layer. The capacitor includes a second conductive layer in contact with the first insulating layer, the second insulating layer in contact with the second conductive layer, and the first conductive layer in contact with the second insulating layer. The second conductive layer includes a composition similar to that of the first semiconductor layer. The first conductive layer and the second conductive layer are configured to transmit visible light.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Daisuke Kurosaki, Yasutaka Nakazawa
  • Patent number: 11532648
    Abstract: A method of manufacturing a display panel and a display panel are provided. A groove is formed on a buffer layer through performing exposure and etching processes, so as to divide the buffer layer into independent units. A gate insulating layer, a dielectric layer, and a passivation layer are converted from continuous layers to independent layers on the buffer layer. Therefore, heterogeneous interface stress accumulated in the independent unit is reduced, it prevents the deformation of the glass substrate, protects the glass substrate, reduces fragmentation phenomenon, and improves process reliability and yield.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: December 20, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaohui Nie
  • Patent number: 11527557
    Abstract: The present application provides an array substrate and a display device. The array substrate includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes at least two first conductive members disposed side by side in the bonding area. The second conductive layer includes at least two second conductive members; each of the second conductive members is provided corresponding to and electrically connected to each of the first conductive members, and at least two of the second conductive members and at least two of the first conductive members are electrically connected through a same via-hole on the insulating layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 13, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Xiaojin He, Chengcai Dong, Ilgon Kim
  • Patent number: 11527419
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Patent number: 11527450
    Abstract: A test element group (TEG) test key of an array substrate and a display panel thereof are provided. The TEG test key of the array substrate includes a glass substrate, a multi-buffer layer, an active layer, a gate insulating layer, a gate electrode layer, an interlayer insulating layer, a source and drain electrode layer, and an organic planarization layer stacked in sequence. The TEG test key of the array substrate is defined with two test zones and a connecting zone, and each test zone is provided with a groove exposing the gate electrode layer. The gate electrode layer in the test zones is electrically connected to the source and drain electrode layer in the connecting zone.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 13, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Gang Tan
  • Patent number: 11522087
    Abstract: The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: December 6, 2022
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 11522088
    Abstract: The disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate layer, a gate layer, an insulating layer, and an active layer. The gate layer is disposed on the substrate layer and includes a first gate layer and a second gate layer. The second gate layer is disposed on a surface of the first gate layer. The insulating layer covers the gate layer and the substrate layer. The active layer is disposed on a surface of the insulating layer away from the gate layer. The active layer includes a first layer section and a second layer section connected to the first layer section, and a surface of the second layer section is above a surface of the first section layer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 6, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Huafei Xie