Abstract: A semiconductor device includes a semiconductor layer including first and second regions and a third region therebetween, a gate insulating layer between the third region and a gate electrode, first and second electrodes connected to the first and second regions in a first direction, a first conductive layer between the first region and the first electrode and/or between the second region and the second electrode. The first conductive layer includes a metal element, aluminum, and nitrogen, and has first and second portions. An atomic concentration of the metal element is higher than that of aluminum in the first portion. An atomic concentration of aluminum is higher than that of the metal element in the second portion. The device further includes a second conductive layer between the oxide semiconductor layer and the first conductive layer. The second conductive layer includes oxygen and at least one of indium, zinc, tin, and cadmium.

Abstract: The present invention discloses a sensor based on a field effect transistor (FET) with nano-tapes of a carbon-based material, especially graphene (GNR), a semiconductor joint, electrodes and a base gate composed of a carbon-based metallic material for the detection and measurement of low concentrations (nM-pM) of metabolites (biomarkers) in living organisms. The device features a unique nano-tape configuration of a carbon-based material, especially armchair-type graphene (GNR) (Armchair) in the semiconductor gasket and electrodes, which favors the manufacture of high-density nanosensor arrangements. The device features bifunctional ligaments based on pyrene compounds bound to the semiconductor joint and covalently the target analyte, generating the mechanical, chemical and electronic stability of the detected signal.

Abstract: The present disclosure provides a display device comprising: a first thin film transistor including a first semiconductor pattern disposed on a substrate and comprising poly-silicon, and a first gate electrode; a middle layer on the first gate electrode; a second thin film transistor including a second semiconductor pattern disposed on the middle layer and comprising an oxide semiconductor, and a second gate electrode; and a storage capacitor including first to fourth storage electrodes overlapping with each other.

Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.

Abstract: According to one embodiment, a display device includes a first insulating layer, a first source line and a second source line, an organic insulating layer including a contact hole, a drain electrode located on the first insulating layer and exposed from the organic insulating layer in the contact hole, a conductive material covering the drain electrode in the contact hole, a second insulating layer located on the organic insulating layer, and a pixel electrode located above the second insulating layer and in the contact hole, and electrically connected to the drain electrode, the conductive material being in contact with the first insulating layer exposed from the organic insulating layer in the contact hole.

Abstract: Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Abstract: Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer (7) including Ta or the like is inserted beneath a hard mask layer (8).

Abstract: A memory includes a transistor and a magnetic tunnel junction (MTJ) storage element, a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor using a conduction structure, wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers, the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole, the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer, the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

Abstract: An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Abstract: Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

Abstract: A transistor includes a first gate electrode, a first capping layer, a crystalline semiconductor oxide layer, a second capping layer, a first gate dielectric layer, and source/drain contacts. The first capping layer, the crystalline semiconductor oxide layer, and the second capping layer are sequentially disposed over the first gate electrode. Sidewalls of the second capping layer are aligned with sidewalls of the crystalline semiconductor oxide layer. The first gate dielectric layer is located between the first gate electrode and the first capping layer. The source/drain contacts are disposed on the second capping layer. The crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.

Abstract: Provided is a solid-state imaging device including: a photoelectric conversion unit that converts received light into an electric charge; a memory unit that holds the electric charge; and a light blocking unit that blocks light. The photoelectric conversion unit and the memory unit are formed in a semiconductor substrate. The light blocking unit is formed as a lid portion on the back surface side of the semiconductor substrate, which is the side at which light to the memory unit enters, and is also continuously formed including a first embedded portion and a second embedded portion that are embedded between the photoelectric conversion unit and the memory unit so as to extend in the semiconductor substrate. The first embedded portion is in a transfer region for transferring the electric charge, and the second embedded portion is outside the transfer region. The lid portion includes at least one recessed structure.

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract: A display device according to an embodiment includes a light blocking layer disposed on a substrate; an oxygen supply layer disposed on and contacting the light blocking layer; a semiconductor layer disposed on the oxygen supply layer; and a light emitting diode electrically connected with the semiconductor layer. The semiconductor layer includes an oxide semiconductor, and the oxygen supply layer includes a metal oxide that includes at least one of indium, zinc, gallium, and tin.

Abstract: The present invention provides a semiconductor device, comprising: a substrate (10); a stack of III-nitride transition layers (11) disposed on the substrate (10), the stack of III-nitride transition layers (11) maintaining an epitaxial relationship to the substrate (10); a first III-nitride layer (121) disposed on the stack of III-nitride transition layers (11); and a second III-nitride layer (122) disposed on the first III-nitride layer (121), the second III-nitride layer (122) having a band gap energy greater than that of the first III-nitride layer (121), wherein the stack of III-nitride transition layers (11) comprises a first transition layer (111), a second transition layer (112) on the first transition layer (111), and a third transition layer (113) on the second transition layer (112), and wherein the second transition layer (112) has a minimum aluminium molar ratio among the first transition layer (111), the second transition layer (112) and third transition layer (113).

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon.

Abstract: A display panel includes: a substrate defining an opening therein; a plurality of light-emitting diodes in a display area surrounding the opening; an encapsulation layer on the plurality of light-emitting diodes, the encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer; a first partition wall and a second partition wall in a non-display area between the opening and the display area in a direction from the display area to the opening; and a plurality of grooves defined above the at least one inorganic insulating layer in the non-display area. The at least one inorganic insulating layer is on the substrate. At least one of the plurality of grooves is defined between the first partition wall and the second partition wall and is covered with the organic encapsulation layer.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.