Patents Examined by Nikolay K Yushin
  • Patent number: 12010843
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 12009401
    Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: June 11, 2024
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 12000045
    Abstract: Described herein is a technique capable of improving characteristics of a film. According to one or more embodiments of the present disclosure, there is provided a technique that includes: (a) performing (a-1) supplying in parallel a metal-containing gas and a reducing gas that contains silicon and hydrogen and is free of halogen to a substrate in a process chamber, and (a-2) exhausting an inner atmosphere of the process chamber; (b) repeatedly performing (a) a first number of times; (c) supplying a nitrogen-containing gas to the substrate in the process chamber and exhausting the inner atmosphere of the process chamber after performing (b); and (d) repeatedly performing (a) a second number of times.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: June 4, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Takuya Joda, Yukinao Kaga, Yoshimasa Nagatomi
  • Patent number: 12004367
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate at least including a pixel area and a hole area; a plurality of sub-pixels arranged on the base substrate and located in the pixel area; a hole in the hole area; a first barrier dam arranged between the sub-pixels and the hole and at least partially surrounding the hole; an organic material layer including at least one film layer, wherein an orthographic projection of the organic material layer on the base substrate falls within the pixel area; and a filling structure, wherein at least a portion of the filling structure is arranged between the hole and the first barrier dam, and the filling structure and the at least one film layer of the organic material layer are located in the same layer and include the same material.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 4, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xin Zhang, Yupeng He, Yang Zhou, Wei Wang, Xiaofeng Jiang, Yu Wang, Lulu Yang, Yiyang Zhang, Guanghui Yang, Jiaming Lu, Rui Hao, Qun Ma, Pu Liu, Liudong Zhu, Qiang Huang, Bin He, Dinan Duan, Haiyong Bai, Xin Li, Ruiqi Wei
  • Patent number: 11996422
    Abstract: An electronic device includes: a capacitor; an insulating layer; at feast one trench provided in the insulating layer; and a first conductive plug, at least part of which is surrounded by the insulating layer. The capacitor includes: a first lower electrode provided along an inner wall of the at least one trench, a dielectric layer provided on the first lower electrode, and an upper electrode provided on the dielectric layer. At least part of the first conductive plug is positioned between an upper surface of the insulating layer and a lowermost portion of the at least one trench.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 28, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Takase, Shunsuke Isono, Yuuko Tomekawa
  • Patent number: 11994810
    Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: May 28, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Li Xiao, Jiao Zhao, Dongni Liu, Minghua Xuan, Haoliang Zheng, Liang Chen, Hao Chen, Zhenyu Zhang, Jing Liu, Qi Qi
  • Patent number: 11997878
    Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate and a first recess. The first recess sequentially extends through a second dielectric layer, a third insulating layer, a first dielectric layer, a second insulating layer, a first insulating layer, an active layer, and a portion of a barrier layer. A bottom surface of the first recess is formed inside the barrier layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 28, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Huihui Zhao, Changbum Park
  • Patent number: 11997883
    Abstract: An organic light emitting diode display device are provided. The organic light emitting diode display device includes: a substrate; a barrier layer, located on a side of the substrate; a first buffer layer, located on a side of the barrier layer; a first semiconductor layer, located on a side of the first buffer layer; a first gate insulating layer, located on a side of the first semiconductor layer; a first gate electrode, located on a side of the first gate insulating layer; a second buffer layer, located on a side of the first gate electrode; a second semiconductor layer, located on a side of the second buffer layer; a second gate insulating layer, located on a side of the second semiconductor layer; a second gate electrode, located on a side of the second gate insulating layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 28, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Yang
  • Patent number: 11990420
    Abstract: An electromagnetic wave shielding sheet according to the present embodiments is an electromagnetic wave shielding sheet for forming an electromagnetic wave shielding layer used for a component-mounting substrate including a substrate, an electronic component and an electromagnetic wave shielding layer, in which the electromagnetic wave shielding sheet includes at least one of a conductive layer before thermal pressing of the electromagnetic wave reflection layer and a conductive layer before thermal pressing of the electromagnetic wave absorption layer, the conductive layer before thermal pressing of the electromagnetic wave reflection layer includes a binder resin and a conductive filler, and the conductive layer before thermal pressing of the electromagnetic wave absorption layer includes a binder resin and an electromagnetic wave absorption filler. The Young's modulus of the conductive layer at 23° C. is set to 10 to 700 MPa.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 21, 2024
    Assignees: ARTIENCE CO., LTD., TOYOCHEM CO., LTD.
    Inventors: Kazunori Matsudo, Ryota Umezawa, Kenji Ando, Tsutomu Hayasaka
  • Patent number: 11984458
    Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a display region and a frame region surrounding the display region. The display region includes a first region and a second region, and the quantity of sub-pixels connected to each gate line in the first region is less than the quantity of sub-pixels connected to each gate line in the second region. The display substrate includes a signal line arranged in the frame region, an orthogonal projection of each gate line in the first region onto a base substrate of the display substrate partially overlaps an orthogonal projection of the signal line onto the base substrate, and a capacitor is formed between the signal line and the gate line in the first region to increase a load capacitance of the gate line in the first region.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: May 14, 2024
    Assignees: Chengdu BOE Optoelectroni cs Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Tinghua Shang, Yang Zhou, Zhengwei Luo
  • Patent number: 11977049
    Abstract: The present invention discloses a sensor based on a field effect transistor (FET) with nano-tapes of a carbon-based material, especially graphene (GNR), a semiconductor joint, electrodes and a base gate composed of a carbon-based metallic material for the detection and measurement of low concentrations (nM-pM) of metabolites (biomarkers) in living organisms. The device features a unique nano-tape configuration of a carbon-based material, especially armchair-type graphene (GNR) (Armchair) in the semiconductor gasket and electrodes, which favors the manufacture of high-density nanosensor arrangements. The device features bifunctional ligaments based on pyrene compounds bound to the semiconductor joint and covalently the target analyte, generating the mechanical, chemical and electronic stability of the detected signal.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: May 7, 2024
    Assignee: PONTIFICIA UNIVERSIDAD JAVERIANA
    Inventors: Andres Jaramillo Botero, Juan Manuel Marmolejo Tejada
  • Patent number: 11978806
    Abstract: A semiconductor device includes a semiconductor layer including first and second regions and a third region therebetween, a gate insulating layer between the third region and a gate electrode, first and second electrodes connected to the first and second regions in a first direction, a first conductive layer between the first region and the first electrode and/or between the second region and the second electrode. The first conductive layer includes a metal element, aluminum, and nitrogen, and has first and second portions. An atomic concentration of the metal element is higher than that of aluminum in the first portion. An atomic concentration of aluminum is higher than that of the metal element in the second portion. The device further includes a second conductive layer between the oxide semiconductor layer and the first conductive layer. The second conductive layer includes oxygen and at least one of indium, zinc, tin, and cadmium.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventor: Hikari Tajima
  • Patent number: 11973089
    Abstract: The present disclosure provides a display device comprising: a first thin film transistor including a first semiconductor pattern disposed on a substrate and comprising poly-silicon, and a first gate electrode; a middle layer on the first gate electrode; a second thin film transistor including a second semiconductor pattern disposed on the middle layer and comprising an oxide semiconductor, and a second gate electrode; and a storage capacitor including first to fourth storage electrodes overlapping with each other.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: April 30, 2024
    Assignee: LG Display Co., Ltd.
    Inventor: Hyunsoo Lim
  • Patent number: 11967669
    Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Bum Han, Young Gil Park, Jung Hwa Park, Na Ri Ahn, Soo Im Jeong, Ki Nam Kim, Moon Sung Kim
  • Patent number: 11961743
    Abstract: Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 16, 2024
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng
  • Patent number: 11963458
    Abstract: Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer (7) including Ta or the like is inserted beneath a hard mask layer (8).
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 16, 2024
    Assignee: TOHOKU UNIVERSITY
    Inventors: Koichi Nishioka, Tetsuo Endoh, Shoji Ikeda, Hiroaki Honjo, Hideo Sato, Sadahiko Miura
  • Patent number: 11960177
    Abstract: According to one embodiment, a display device includes a first insulating layer, a first source line and a second source line, an organic insulating layer including a contact hole, a drain electrode located on the first insulating layer and exposed from the organic insulating layer in the contact hole, a conductive material covering the drain electrode in the contact hole, a second insulating layer located on the organic insulating layer, and a pixel electrode located above the second insulating layer and in the contact hole, and electrically connected to the drain electrode, the conductive material being in contact with the first insulating layer exposed from the organic insulating layer in the contact hole.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 16, 2024
    Assignee: Japan Display Inc.
    Inventor: Makoto Uchida
  • Patent number: 11961842
    Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 11955309
    Abstract: An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zheng-Yang Li, Chian-Chen Kuo, Yi-Cheng Lu, Ji-Fu Kung
  • Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang