Patents Examined by Nikolay K Yushin
  • Patent number: 10847495
    Abstract: A bonding system includes a surface modifying apparatus, a surface hydrophilizing apparatus and a bonding apparatus. The surface modifying apparatus is configured to modify a bonding surface of a first substrate and a bonding surface of a second substrate with plasma. The surface hydrophilizing apparatus is configured to hydrophilize the modified bonding surfaces of the first substrate and the second substrate. The bonding apparatus includes a condensation suppressing gas discharge unit, and is configured to bond the hydrophilized bonding surfaces of the first substrate and the second substrate by an intermolecular force. The condensation suppressing gas discharge unit is configured to discharge a condensation suppressing gas toward a space between a peripheral portion of the bonding surface of the first substrate and a peripheral portion of the bonding surface of the second substrate facing each other.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Nagata, Hiroshi Maeda, Kenji Sugakawa
  • Patent number: 10840081
    Abstract: A substrate liquid processing method includes immersing the substrate in a processing liquid for processing the substrate, detecting a conversion point at which a processing condition of the processing the substrate is changed, and changing the processing condition when the conversion point is detected.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takumi Honda, Kazusige Sano, Hironobu Hyakutake
  • Patent number: 10840088
    Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 10832916
    Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Carl Radens, Kangguo Cheng, Veeraraghavan S. Basker
  • Patent number: 10833158
    Abstract: A technique relates to a semiconductor device. A stack is formed of alternating layers of inserted layers and channel layers on a substrate. Source or drain (S/D) regions are formed on opposite sides of the stack. The inserted layers are converted into oxide layers. Gate materials are formed on the stack.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10832964
    Abstract: A semiconductor structure is disclosed including a semiconductor substrate having two or more fins. The semiconductor structure includes a recessed gate structure having opposing sidewalls located over one of the fins. The semiconductor structure includes a gate spacer disposed on the opposing sidewalls of the recessed gate structure. The semiconductor structure includes a source/drain region disposed between adjacent gate spacers. The semiconductor structure includes a first conductive material disposed on the source/drain region and an interlevel dielectric layer disposed on a top surface of the semiconductor structure defining an opening therein to an exposed top surface of the first conductive material. A width of an upper portion of the opening is greater than the width of the lower portion of the opening. The lower portion of opening is aligned with the first conductive material. The semiconductor structure includes a second conductive material disposed in the opening.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporatior
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Chanro Park, Nicolas Loubet
  • Patent number: 10825795
    Abstract: A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yeong-Seok Kim
  • Patent number: 10825977
    Abstract: A method of manufacturing a thermoelectric converter includes filling each of a plurality of through-holes in each of a plurality of resin films with fillers containing a plurality of thermoelectric material particles. At this time, a part of the filler is extruded from each through-hole. In this state, the plurality of resin films are stacked together. A top-surface protection member having top-surface conductor patterns is stacked on one side of the plurality of resin films. A back-surface protection member having back-surface conductor patterns is stacked on the other side of the plurality of resin films. Thus, an integrated stacked body is formed. The integrated stacked body is then heated and pressurized. A plurality of thermoelectric material particles are thereby sintered to form the first and second thermoelectric members.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 3, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toshikazu Harada, Atusi Sakaida, Toshihisa Taniguchi, Tomohiro Imura, Yuki Sakashita, Hayato Watanabe
  • Patent number: 10818852
    Abstract: Provided are: a light-emitting layer for a perovskite light-emitting device; a method for manufacturing the same; and a perovskite light-emitting device using the same. The method of the present invention for manufacturing a light-emitting layer for a halide perovskite light-emitting device comprises a step of forming a first nanoparticle thin film by coating, on a member for coating a light-emitting layer, a solution comprising halide perovskite nanoparticles including a perovskite nanocrystal structure. Thereby, a nanoparticle light emitter has therein a halide perovskite having a crystal structure in which FCC and BCC are combined; and can show high color purity. In addition, it is possible to improve the luminescence efficiency and luminance of a device by making perovskite as nanoparticles and then introducing the same into a light-emitting layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 27, 2020
    Inventors: Tae-Woo Lee, Sanghyuk Im, Himchan Cho, Young-Hoon Kim
  • Patent number: 10818803
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ali Razavieh
  • Patent number: 10811478
    Abstract: An organic light-emitting diode display device includes a pixel electrode, a pixel-defining layer, an organic emission layer, and a counter electrode. The pixel-defining layer includes an opening partially exposing the pixel electrode. The organic emission layer is disposed on the pixel electrode. The organic emission layer is disposed in the opening. The counter electrode is disposed on the organic emission layer. The counter electrode opposes the pixel electrode. The pixel-defining layer includes a first pixel-defining layer and a second pixel-defining layer. The first pixel-defining layer is disposed on the pixel electrode and includes an inorganic material. The second pixel-defining layer is disposed on the first pixel-defining layer and includes an organic material. A sidewall of the first pixel-defining layer that is closest to the opening is aligned with a sidewall of the second pixel-defining layer that is closest to the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Won Choi, Tae Wook Kang, Kyeong Su Ko, Sang Gab Kim, Tae Sung Kim, Joon Geol Lee, Hyun Min Cho
  • Patent number: 10811502
    Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP USA, Inc.
    Inventors: Vishnu Khemka, Tanuj Saxena, Ganming Qin, Raghuveer Vankayala Gupta, Mark Edward Gibson, Moaniss Zitouni
  • Patent number: 10811326
    Abstract: A method of detecting undesired surface effects while lasing a semiconductor during a laser marking, (dicing, fuse cutting or otherwise) process. A detection device is placed near the site of semiconductor lasing to detect erroneous laser markings resulting in the undesired surface effects. Upon identifying such a condition, lasing may be interrupted in-process.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Michael Garbe
  • Patent number: 10811491
    Abstract: A display substrate and a method of manufacturing the same, and a display panel are provided. The display substrate includes: a base substrate, and a first electrode, a first auxiliary electrode, a boss, a pixel definition layer, an organic functional layer and a second electrode provided on the base substrate. The first auxiliary electrode includes a first conductive connection part contacting a side surface of the boss; the pixel definition layer is provided with a pixel accommodating hole and a slot; the organic functional layer is electrically connected with the first electrode through the pixel accommodating hole; and the second electrode is electrically connected with the first conductive connection part through the slot, so that the second electrode is connected with the first auxiliary electrode in parallel.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 20, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xing Fan
  • Patent number: 10797139
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Patent number: 10796913
    Abstract: A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 6, 2020
    Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD.
    Inventor: Hong Lin
  • Patent number: 10797681
    Abstract: A method of fabricating packaged electronic components with improved yield and at lower unit cost; the method comprising the steps of obtaining an active membrane layer on a carrier substrate, depositing a front electrode onto a front of the active membrane layer, obtaining an inner front section including at least a silicon handle or wafer, attaching an inner front end section to an outer surface of the front electrode, detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited, patterning the active membrane layer into an array of at least one island of membrane, selectively removing the front electrode and bonding layer, selectively applying an inner passivation layer, and selectively depositing a back electrode layer on the thus exposed back surface of the active membrane.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Zhuhai Crystal Resonance Technologies Co., Ltd.
    Inventors: Dror Hurwitz, BawChing Perng, Duan Feng
  • Patent number: 10797260
    Abstract: Embodiments of the present disclosure provide an OLED substrate and a fabrication method thereof, and a display panel. The method for fabricating an OLED substrate includes: forming an auxiliary cathode in a display region on a base substrate; forming an organic material functional layer in the display region on the base substrate where the auxiliary cathode is formed; applying a voltage to the auxiliary cathode to deform the auxiliary cathode, such that the organic material functional layer is ruptured by the deformed auxiliary cathode to form a connection channel; and forming a cathode in the display region on the base substrate where the organic material functional layer is formed. The cathode is electrically connected to the auxiliary cathode at the connection channel.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 6, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dini Xie, Wei Li, Xiaojin Zhang
  • Patent number: 10797114
    Abstract: An organic light-emitting display apparatus and a method of manufacturing the same are provided. An organic light-emitting display apparatus includes a first light-emitting unit including a first color light-emitting layer on an area of a substrate, a second light-emitting unit including a second color light-emitting layer spaced apart from the first color light-emitting layer, and a third light-emitting unit including a third color light-emitting layer as a common layer corresponding to both areas of the first color light-emitting layer and the second color light-emitting layer, and the first color light-emitting layer includes a lower light-emitting layer and an upper light-emitting layer that are stacked to have a multilayered structure.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Changmin Lee, Juwon Lee, Hyomin Ko, Sanggyun Kim
  • Patent number: 10781515
    Abstract: There is provided a method of forming a predetermined film by alternately supplying a film-forming raw material gas and a reaction gas onto a workpiece by an atomic layer deposition (ALD), the method including: beginning an ALD-based film formation at a first temperature at which an adsorption of the film-forming raw material gas occurs; continuing the ALD-based film formation while increasing the first temperature; and completing the ALD-based film formation at a second temperature at which a decomposition of the film-forming raw material gas occurs.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 22, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kyungseok Ko, Hiromi Shima, Eiji Kikama, Keisuke Suzuki