Patents Examined by Nikolay K Yushin
  • Patent number: 11430844
    Abstract: An array substrate, a manufacturing method thereof and an organic light emitting diode display device are provided. The manufacturing method of the array substrate includes forming a first thin film transistor including a first semiconductor pattern, including forming a first electrode pattern including a first source electrode and a first drain electrode and a second electrode pattern including a first auxiliary source electrode and a first auxiliary drain electrode respectively through two patterning processes; forming a second thin film transistor including forming a second source electrode and a second drain electrode through one patterning process. The second electrode pattern, the second source electrode and the second drain electrode are formed in the same patterning process, the first electrode pattern is connected with the first semiconductor pattern.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: August 30, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Yang
  • Patent number: 11424271
    Abstract: Various examples are provided related to hydrogen plasma treatment of hafnium oxide. In one example, a method includes depositing a monolayer of a precursor on a first oxide monolayer; forming a second oxide monolayer by applying an oxygen (O2) plasma to the monolayer of the precursor; and creating oxygen vacancies in the second oxide monolayer by applying a hydrogen (H2) plasma to the second oxide monolayer. In another example, a device includes a hafnium oxide (HfO2) based ferroelectric thin film on a first side of a substrate and an electrode layer disposed on the HfO2 based ferroelectric thin film opposite the substrate. The HfO2 film includes a plurality of oxide monolayers including at least one HfO2 monolayer, each of the plurality of oxide monolayers having oxygen vacancies distributed throughout that oxide monolayer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 23, 2022
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Toshikazu Nishida, Saeed Moghaddam, Glen H. Walters, Aniruddh Shekhawat
  • Patent number: 11424334
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Takahiro Iguchi, Yukinori Shima, Kenichi Okazaki
  • Patent number: 11417689
    Abstract: The present application proposes a display panel, which includes a substrate, and a first thin film transistor and a second thin film transistor disposed on the substrate at intervals, wherein a first metal layer is disposed on a side of the oxide semiconductor layer away from the third gate, a first interlayer insulating layer is disposed between the first metal layer and the oxide semiconductor layer, a second gate insulating layer is disposed on a side of the first metal layer away from the oxide semiconductor layer, and the first metal layer includes a second gate corresponding to the oxide semiconductor layer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 16, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huihui Zhao
  • Patent number: 11417773
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor is provided in contact with a top surface of the first oxide. The second conductor is provided in contact with the top surface of the first oxide. The first insulator is provided over the first conductor and the second conductor. The second oxide is provided in contact with the top surface of the first oxide. The second insulator is provided over the second oxide. The third conductor is provided over the second insulator. The first insulator has a function of inhibiting diffusion of oxygen. The first oxide includes indium, an element M (M is gallium, yttrium, or tin), and zinc. The first oxide includes a first region overlapping with the third conductor.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 16, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Erika Takahashi, Hiroaki Honda, Kentaro Sugaya, Shinya Sasagawa
  • Patent number: 11414776
    Abstract: An electrochemical processing device includes a current supply unit, a jig, and a controller. The current supply unit provides current for an electrochemical process. The jig includes a clamping region for clamping a substrate, a plurality of processing electrodes disposed in the clamping region and connected to the current supply unit, and a plurality of measuring electrodes disposed in the clamping region. The controller is connected to the plurality of measuring electrodes. When the jig clamps the substrate to perform the electrochemical process, the controller provides a measuring current to the measuring electrode to measure the thickness of the metal layer of the substrate.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 16, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ming Lin, Ming-Huei Yen
  • Patent number: 11411101
    Abstract: A TFT substrate and a manufacturing method thereof are provided. In the manufacturing method, a metal oxide semiconductor layer is irradiated with UV light by using a gate as a shielding layer, such that a portion of the metal oxide semiconductor layer irradiated by the UV light is conductorized to form a source, a drain, and a pixel electrode, and a portion of the metal oxide semiconductor layer shielded by the gate still retains semiconductor properties to form a semiconductor channel. The invention achieves the alignment of the source and the drain with the gate by processes of self-alignment of the gate and conductorization of the metal oxide semiconductor layer, and can effectively control an overlapping region of the source and drain and the gate. Thereby, the parasitic capacitance is reduced, and the display quality is improved. Also, the manufacturing method is simple, and the production efficiency is improved.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 9, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xianwang Wei
  • Patent number: 11404579
    Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. In the array substrate, a functional layer disposed between an active layer and a gate insulating layer protects the active layer during etching of the active layer, which prevents the active layer from damage and conducts a source/drain layer and the active layer, so that transistors in the array substrate work normally, solving the technical problem that current display panels damage the active layer during a preparation process, which causes performance of thin film transistors to decrease.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 2, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Chuanbao Luo, Macai Lu
  • Patent number: 11404447
    Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 2, 2022
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Patent number: 11404446
    Abstract: A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 2, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Juncheng Xiao, Chao Tian, Yanqing Guan, Haiming Cao
  • Patent number: 11393853
    Abstract: An array substrate and a manufacturing method thereof are disclosed. The method includes: forming a first thin film transistor which includes a first semiconductor layer, a first gate electrode, a first drain electrode and a first source electrode; forming a second thin film transistor which includes a second semiconductor layer, a second gate electrode, a second drain electrode and a second source electrode; and forming a dielectric layer which spaces the first semiconductor layer apart from the second semiconductor layer; the method further includes: processing the same layer to form at least one selected from the group consisting of the first gate electrode, the first drain electrode and the first source electrode, at least one selected from the group consisting of the second gate electrode, the second drain electrode and the second source electrode, and the dielectric layer by the same layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 19, 2022
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Kui Gong, Biliang Dong, Xianxue Duan, Zhihai Zhang
  • Patent number: 11393849
    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: July 19, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Masamitsu Yamanaka, Hitoshi Takahata
  • Patent number: 11387260
    Abstract: A manufacturing method of a TFT substrate is a manufacturing method of a TFT substrate in which each of a source electrode and a drain electrode includes a lower source metal layer and an upper source metal layer. The manufacturing method of the TFT substrate includes the steps of: forming an upper source metal layer by etching an upper conductive film with the first resist layer as an etching mask; forming a lower source metal layer by etching a lower conductive film; removing the first resist layer and forming a second resist layer covering the upper source metal layer; and forming a source contact portion and a drain contact portion by etching a contact layer by dry etching with the second resist layer as an etching mask.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 12, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 11380716
    Abstract: An array substrate and manufacturing method thereof are provided. The array substrate includes: a substrate; a first gate electrode insulating layer disposed on the substrate, wherein the first gate electrode insulating layer has a recess therein; a gate electrode layer disposed in the recess of the first gate electrode insulating layer; a second gate electrode insulating layer covering the first gate electrode insulating layer and the gate electrode layer; and an active layer disposed on the second gate electrode insulating layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 5, 2022
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Meng Chen
  • Patent number: 11374027
    Abstract: A manufacturing method of a thin film transistor substrate and a thin film transistor substrate are provided. In the manufacturing method of the thin film transistor substrate, a buffer layer, a metal oxide semiconductor layer, and a first insulating layer are sequentially deposited on a substrate, and then the first insulating layer and the metal oxide semiconductor layer are patterned according to a pattern of an active layer. The metal oxide semiconductor layer forms the active layer. A second insulating layer and a gate metal layer are then sequentially deposited. The first insulating layer and the second insulating layer together form a gate insulating layer. The first insulating layer can be used to protect the metal oxide semiconductor layer, such that defects on a contact surface between the active layer and the gate insulating layer are reduced, thereby improving the stability of a device.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 28, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Macai Lu
  • Patent number: 11367792
    Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 21, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Song, Liangchen Yan, Ce Zhao, Heekyu Kim, Yuankui Ding, Leilei Cheng, Yingbin Hu, Wei Li, Guangyao Li, Qinghe Wang
  • Patent number: 11367815
    Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Bum Han, Young Gil Park, Jung Hwa Park, Na Ri Ahn, Soo Im Jeong, Ki Nam Kim, Moon Sung Kim
  • Patent number: 11362113
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 14, 2022
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Toshihide Jinnai, Ryo Onodera, Akihiro Hanada
  • Patent number: 11361978
    Abstract: The present disclosure relates to high pressure processing apparatus for semiconductor processing. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 14, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Adib M. Khan, Qiwei Liang, Sultan Malik, Srinivas D. Nemani
  • Patent number: 11362118
    Abstract: The present invention provides an array substrate, a manufacturing method thereof, and a display panel. Orthographic projections of channel layers of two types of thin film transistors in a design of a driving circuit on the array substrate at least partially overlap, that is, two thin film transistors are stacked on top of each other, thereby facilitating a narrow border design of the display panel. In addition, a channel layer of one of the thin film transistors is an amorphous oxide semiconductor layer, which can reduce node leakage in the driving circuit, which is conducive to improving circuit stability and reducing power consumption.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 14, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Juncheng Xiao, Chao Tian, Yanqing Guan, Haiming Cao