Abstract: A method of manufacturing a display apparatus according to an exemplary embodiment includes the steps of forming a plurality of light emitting diode chips on a first manufacturing substrate, coupling the plurality of the light emitting diode chips onto a second manufacturing substrate, separating the first manufacturing substrate from the plurality of the light emitting diode chips, and transferring the plurality of light emitting diode chips coupled onto the second manufacturing substrate to a substrate including first and second substrate electrodes.

Abstract: A power inverter module includes a base module having a plurality of electrically conductive layers, including a first conductive layer, a second conductive layer and a third conductive layer. A first terminal is operatively connected to the first conductive layer at a first end and a second terminal is operatively connected to the second conductive layer at the first end. An isolation sheet is sandwiched between the first and second terminals. The first terminal and the second terminal include a respective proximal portion composed of a first material and a respective distal portion composed of a second material. At least one of the first terminal and the second terminal is bent to create an overlap zone such that a gap between the first terminal and the second terminal in the overlap zone is less than a threshold distance. The power inverter module is configured to reduce parasitic inductance.

Abstract: A method of forming a nitride film wherein (a) a silane-based gas is supplied to a processing chamber through a gas supply port; (b) a nitrogen radical gas from a radical generator is supplied to the processing chamber through a radical gas pass-through port; and (c) the silane-based gas supplied in (a) is reacted with the nitrogen radical gas supplied in (b), without causing a plasma phenomenon in the processing chamber, to form a nitride film on a wafer.

Abstract: The disclosure discloses a light-emitting device, a pixel circuit, a method for controlling the pixel circuit, an array substrate and a display device, where the light-emitting device includes a cathode, an anode and a light-emitting layer, where: the cathode includes a first sub-cathode and a second sub-cathode, both of which are arranged at a same layer; the anode includes a sub-anode and a second sub-anode, both of which are arranged at a same layer; and the light-emitting layer is located between the cathode and the anode.

Abstract: A display device includes a substrate, at least one light emitting element and at least two driving arrays. The at least one light emitting element is disposed on the substrate, and the at least one light emitting element has a first terminal and a second terminal. The at least two driving arrays are disposed on the substrate, and one of the at least two driving arrays is electrically connected to the first terminal of the at least one light emitting element.

Abstract: A display panel is provided and includes a display region including a plurality of sub pixel regions arranged in an array, wherein each of the sub pixel regions comprises a light emitting region and a non-light emitting region; a black array layer formed in the non-light emitting regions, the black array is used to shield the metal layer to reflect and absorb the environment light, to improve a light output rate and to improve a contrast ratio of the display device.

Abstract: The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.

Abstract: A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.

Abstract: The present disclosure provides a display panel, a manufacturing method of the display panel, and a display device. The manufacturing method includes: forming an auxiliary cathode layer; forming at least one tip structure on the auxiliary cathode layer; forming a main cathode layer, wherein the at least one tip structure is between the auxiliary cathode layer and the main cathode layer; and forming at least one connection between the main cathode layer and the auxiliary cathode layer by discharging at the at least one tip structure, wherein the at least one connection is electrically connected to the main cathode layer and the auxiliary cathode layer respectively.

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

Abstract: Provided is an optical film 10 including a light-transmitting base material 11 and a light-transmitting functional layer 12 provided on one surface of the light-transmitting base material 11, wherein the optical film 10 has a spectral transmittance of less than 1% at a wavelength of 380 nm, a spectral transmittance of 10% or more and less than 60% at a wavelength of 410 nm, and a spectral transmittance of 70% or more at a wavelength of 440 nm, and wherein the light-transmitting functional layer 12 has a film thickness of 9 ?m or less.

Abstract: A chip on film package structure including a flexible film and a chip is provided. The flexible film includes a main body and a first wing body. The main body includes a main bonding portion configured to be bonded to a first substrate. The first wing body includes a first extending part and a first bent part. The first extending part is extended from a side of the main body. The first bent part is configured to be bent to a second substrate and having a first wing bonding portion. The first wing bonding portion is configured to be bonded to the second substrate. The first substrate and the second substrate are stacked on top of each other. The chip mounted on and electrically connected to the main body. A display device is also provided.

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

Abstract: A problem to be solved by the present invention is to secure a creepage distance while maintaining miniaturization. A power converter according to the present invention includes a positive electrode side conductor, a negative electrode side conductor, and an insulating member disposed between the positive electrode side conductor and the negative electrode side conductor, in which the positive electrode side conductor or the negative electrode side conductor includes a main surface on a side opposite to a surface in contact with the insulating member, a side surface connected to the surface in contact with the insulating member, and an inclined surface forming an obtuse angle with respect to each of the main surface and the side surface, and the insulating member includes a protrusion formed so as to overlap with the side surface and the inclined surface as viewed in a direction perpendicular to the side surface.

Abstract: In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.

Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90, a first terminal that projects outward from the sealing part 90 and a connector 51 that has a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75, and a proximal end part 45 connected to the first terminal via a conductor layer 75. The head part 40 has a single first projection part 41 that projects toward the electronic element 95. The first projection part 41 sinks into the conductive adhesive 75 and comes into point contact with the front surface of the electronic element 95. The proximal end part 45 has a plurality of protrusion parts 49 or a support surface 46, contacting the conductor layer 70.

Abstract: A method for electron beam lithography. The method may comprise fabricating a multi-layer mask and interposing the multi-layer mask between an electron beam and an energy-sensitive layer to thereby expose the energy-sensitive layer to the electron beam through the mask. Fabricating the multi-layer mask may comprises providing a first mask layer fabricated from a first mask material (e.g. silicon nitride) which defines one or more feature apertures corresponding to features of interest and coating an electron-energy-reducing material (e.g. gold) onto the first mask layer to thereby provide a second mask layer.

Abstract: Provided is a display device. The display device includes a flexible display panel configured to display an image, and a window disposed on a display surface of the flexible display panel. The window includes a first protection layer, a thin film glass layer disposed on the first protection layer, and a second protective layer disposed on the thin film glass layer.