Abstract: A photoelectric conversion element and an optical sensor including the same are disclosed. The photoelectric conversion element may include a plurality of lattice stacks repeatedly stacked on top of each other on a substrate and configured to have an effective band gap. The plurality of lattice stacks may each include a first active layer and a second active layer on the first active layer. The first active layer may include a first two-dimensional material having a first band gap. The second active layer may include a second two-dimensional material having a second band gap not overlapping the first band gap. An effective band gap may be adjusted based on the first two-dimensional materials and thicknesses of the first active layer and the second active layer and a number of times of plurality of lattice stacks.

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

Abstract: Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.

Abstract: A correlated electron material device is described to comprise a conductive substrate and a layer of a correlated electron material disposed over the conductive substrate. The layer of correlated electron material may comprise a metal rich transition or other metal compound, and at least a portion of anion vacancies within the metal rich transition or other metal compound are occupied by an electron back-donating extrinsic ligand for the metal rich transition or other metal compound. Under certain conditions, the electron back-donating extrinsic ligand occupying anion vacancies may be activated so as to impart particular switching characteristics in the correlated electron material device.

Abstract: A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.

Abstract: The present disclosure relates to a device that includes, in order, an emitter layer, a quantum well, and a base layer, where the emitter layer has a first bandgap, the base layer has a second bandgap, and the first bandgap is different than the second bandgap by an absolute difference greater than or equal to 25 meV.

Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.

Abstract: A composition and method for using the composition in the fabrication of an electronic device are disclosed. Compounds, compositions and methods for depositing a high quality silicon nitride or carbon doped silicon nitride.

Abstract: The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.

Abstract: A method for manufacturing a display device includes preparing a target panel including a first substrate and a second substrate disposed on one surface of the first substrate, the target panel including a sealing area between the first substrate and the second substrate, making sealing light be incident in the sealing area and receiving at least a part of the sealing light reflected from the sealing area, generating first data including at least one parameter of intensity, energy, current, and voltage, and determining whether sealing is defective by comparing the first data and prestored second data.

Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.

Abstract: In a semiconductor device using a wide bandgap semiconductor material having a bandgap larger than that of silicon, reliability of the semiconductor device is improved by achieving a structure in which electric field strength in the vicinity of an outer end portion of a semiconductor chip is relaxed. A side surface of the semiconductor chip CHP1a is formed of a region R1 including a first corner, a region R2 including a second corner, and a region R3 interposed between the region R1 and the region R2. At this point, in a case of defining a minimum film thickness of a high electric field-resistant sealing member MR in the region R3 as t1 and defining a maximum film thickness of the high electric field-resistant sealing member MR in the region R1 as t2, a relation of t2?1.5×t1 is satisfied.

Abstract: Provided are: a light-emitting layer for a perovskite light-emitting device; a method for manufacturing the same; and a perovskite light-emitting device using the same. The method of the present invention for manufacturing a light-emitting layer for a halide perovskite light-emitting device comprises a step of forming a first nanoparticle thin film by coating, on a member for coating a light-emitting layer, a solution comprising halide perovskite nanoparticles including a perovskite nanocrystal structure. Thereby, a nanoparticle light emitter has therein a halide perovskite having a crystal structure in which FCC and BCC are combined; and can show high color purity. In addition, it is possible to improve the luminescence efficiency and luminance of a device by making perovskite as nanoparticles and then introducing the same into a light-emitting layer.

Abstract: Disclosed herein are light emitting diodes (LEDs) having a high efficiency. A light emitting diode including an active light emitting layer within a semiconductor layer is provided. The semiconductor layer has a mesa shape. The light emitting diode also includes a substrate having a first surface on which the semiconductor layer is positioned and an outcoupling surface opposite to the first surface. Light generated by the active light emitting layer is incident on the outcoupling surface and propagates toward an optical element downstream of the outcoupling surface. The light emitting diode also includes a first anti-reflection coating adjacent to the outcoupling surface; an index-matched material between the outcoupling surface and the optical element, wherein an index of refraction of the index-matched material is greater than or equal to an index of refraction of the optical element; and/or secondary optics adjacent to the outcoupling surface.

Abstract: A method for manufacturing a micro light-emitting diode array substrate is disclosed. The method includes: providing a drive substrate comprising a plurality of sub-pixel regions, the plurality of sub-pixel regions being configured for bearing micro light-emitting diodes of different colors, and epitaxial layers of the micro light-emitting diodes of different colors having different thicknesses; providing a base substrate, forming a plurality of micro light-emitting diodes on the base substrate, and transferring micro light-emitting diodes of same color on the base substrate as a whole onto the drive substrate; repeating the transferring process in a sequence that the thicknesses of the epitaxial layers of the micro light-emitting diodes gradually increase, until each sub-pixel region in pixel units is provided with one of the micro light-emitting diodes having same color as the each sub-pixel region.

Abstract: A method includes preparing a circuit board that includes a first metal pattern over a first face side of the substrate, a first electrode in a periphery of the first metal pattern, a second electrode over a second face side of the substrate, and a second metal pattern thermally connected to the first metal pattern and in which an electronic device is fixed on the first metal pattern and an electronic component is electrically connected to the second electrode, and connecting the first electrode and a third electrode of the electronic device by a bonding wire with the electronic device being heated. By a board support stage, the electronic device is heated by transferring heat to the electronic device via the second and then first metal pattern with the circuit board being supported to form a space including the electronic component between the second face and the board support stage.

Abstract: A method for producing at at least an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a substrate having at least one aperture, applying at least one semiconductor chip to the substrate, arranging barrier structures provided that the barrier structures are not already part of the substrate, wherein the semiconductor chip is spaced apart from the barrier structures as seen in a side cross-section, applying an auxiliary carrier at least to a main radiation exit surface and to the barrier structures, introducing a casting material via the at least one aperture in the substrate so that the casting material is arranged between the barrier structures and the semiconductor chip and between the substrate and the auxiliary carrier, and curing the casting material.

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

Abstract: In a method of manufacturing a semiconductor device, a first layer having an opening is formed over a substrate. A second layer is formed over the first layer and the substrate. A photo resist pattern is formed over the second layer above the opening of the first layer. The photo resist pattern is reflowed by a thermal process. An etch-back operation is performed to planarize the second layer.