Abstract: Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.

Abstract: The invention provides a TFT array substrate and display panel. The TFT array substrate comprises: a patterned metal oxide active layer, a patterned gate metal layer, and a patterned source/drain metal layer; and further comprises at least a patterned hydrogen-absorbing metal layer, a dielectric layer is disposed between the hydrogen-absorbing metal layer and the patterned metal oxide active layer. The TFT array substrate and display panel of the invention can reduce reaction between the hydrogen atoms and the active layer of metal oxide TFT to achieve improving reliability of TFT.

Abstract: A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.

Abstract: A method for transferring light emitting elements precisely during manufacture of display panels includes providing light emitting elements; providing a first electromagnetic plate defining magnetic adsorption positions; providing a receiving substrate defining receiving areas; energizing the first electromagnetic plate to magnetically adsorb one light emitting element at one adsorption position; facing the first electromagnetic plate to the receiving substrate; and transferring the light emitting elements to one receiving area of the receiving substrate.

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

Abstract: Some embodiments may include a porous silicon carbide substrate plugged with dielectric material, the porous silicon carbide substrate including a first side to couple to a heat source and a second side to couple to an electrically conductive surface, wherein the second side is opposite the first side; wherein in the case that an opening on the area of the first side forms a channel with an opening on an area of the second side, a portion of the dielectric material located in the channel is arranged to prevent an electrical short from forming through the porous silicon carbide substrate to the electrically conductive surface. In some examples, the heat source may be one or more semiconductor laser diode chips. Other embodiments may be disclosed and/or claimed.

Abstract: The present disclosure provides a display panel including a substrate; and a plurality of pixel units arranged on the substrate; wherein each of the plurality of pixel units includes a plurality of sub-pixel units including at least one first type of sub-pixel unit; each of the plurality of sub-pixel units includes a light emitting layer; the at least one first type of sub-pixel unit includes a first light processing layer; the first light processing layer includes at least a light diffusion material and a light conversion material mixed with each other; and the first light processing layer is located on a side of a light emitting surface of the light emitting layer at the at least one first type of sub-pixel unit. By the above-mentioned manner, the uniformity of light conversion by the light emitting layer may be improved, thereby the display effect of the display panel may be improved.

Abstract: Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure.

Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

Abstract: A phosphor carrier assembly includes a substrate, a thermal or UV activated release adhesive, a layer containing a pixelated phosphor array, and a partially cured or highly viscous adhesive. The phosphor pixels on the carrier are typically all of the same color. In formation of a phosphor converted LED array the phosphor pixels on the carrier assembly are aligned with and placed in contact with corresponding LED pixels in an array of pixelated LED dice. Selected phosphor pixels on the carrier assembly may then be attached to corresponding LED pixels, and released from the substrate, by powering (activating) the corresponding LED pixels to heat the selected phosphor pixel to a temperature that releases the thermal release adhesive and that cures or partially cures the adhesive on the selected phosphor pixels in contact with the corresponding LED pixels.

Abstract: A light emitting diode (LED) includes: a device substrate; a first semiconductor layer above the device substrate, and doped with an n-type dopant; a second semiconductor layer above the first semiconductor layer, and doped with a p-type dopant; an active layer between the first semiconductor layer and the second semiconductor layer and configured to provide light; a transparent electrode layer adjacent to an upper part of the second semiconductor layer; and a first electrode pad and a second electrode pad between the device substrate and the first semiconductor layer, the first electrode pad electronically connected with the first semiconductor layer and the second electrode pad electrically connected with the second semiconductor layer, wherein light provided by the active layer is irradiated to an outside in a direction from the active layer to the second semiconductor layer.

Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor.

Abstract: A thin-film transistor and a manufacturing method for the same are disclosed.

Abstract: A semiconductor memory device, with which a manufacturing method is associated, includes a substrate. The semiconductor memory device also includes a source structure disposed on a first region of the substrate, memory cell strings connected to the source structure, and a capacitor structure disposed on a second region of the substrate. The capacitor structure is spaced apart from the source structure in a horizontal direction.

Abstract: This disclosure relates to the field of display technologies, and discloses an OLED display panel, a method for fabricating the same, and a display device, and the OLED display device includes: a first substrate; a pixel definition layer located on the first substrate, and including a plurality of hollow light-emitting areas, and first recessed sections located between adjacent light-emitting areas; a cathode layer located on a side of the pixel definition layer away from the first substrate, and comprising corresponding second recessed sections corresponding in position to the first recessed sections; and electrically conductive sections located on a side of the cathode layer away from the pixel definition layer, and located in the second recessed sections.

Abstract: The TG-SA ITZO TFT comprises a substrate, a buffer layer, an ITZO thin film, a gate dielectric layer, a conductive thin film, a passivation layer, gate, source and drain contact electrodes. The transistor has a TG-SA structure, which can address the issues of larger parasitic capacitance and weaker device scalability in a traditional bottom-gate counterpart. When depositing the gate dielectric layer and the passivation layer, different gas sources and annealing conditions are used, such that the ITZO thin film region contacted with and covered by the gate dielectric layer shows a high-resistivity state, the ITZO thin film region contacted with and covered by the passivation layer shows a low-resistivity state, thereby forming a high-resistivity channel region and low-resistivity conductive source and drain regions, and addressing the thermal instability issue.