Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

Abstract: A semiconductor device includes an electronic circuit, an interconnection contact such as a solder ball, and a plate configured to concentrate magnetic flux to a predetermined area. The plate is electrically conductive, and it is electrically connected to the electronic circuit.

Abstract: The present invention provides an array substrate and manufacturing method thereof. The array substrate includes a thin film transistor including a gate, an active layer, a gate insulation layer, a source, and a drain. The active layer includes a first active layer and a second active layer laminated with one another, and material of the first active layer and the second active layer are different, to increase the on-state current of the thin film transistor. The present invention increases the on-state current by reducing a contact barrier with the gate insulation layer or reducing a depletion area of the active layer.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of vertical fins on a substrate, and forming at least two dummy gates across the plurality of vertical fins. The method further includes forming a masking block on one of the at least two dummy gates, and removing the portions of the at least two dummy gates not covered by the masking block, wherein the portion of the one dummy gate covered by the masking block forms a dummy gate plug. The method further includes forming a gate dielectric layer on the exposed surfaces of the plurality of vertical fins and dummy gate plug, and forming a conductive gate layer on the gate dielectric layer, wherein the dummy gate plug physically separates two active gate structures.

Abstract: Provided is an electronic device including a display panel including a base substrate, pixels, a first insulation layer, and panel pads spaced along a first direction from pixels and each arranged along a second direction crossing the first direction, a circuit board disposed on the display panel and connected to panel pads, and an adhesive interconnect layer disposed between the display panel and the circuit board and electrically connecting the display panel and the circuit board. The circuit board includes a flexible substrate including a top surface facing the base substrate, output pads disposed on the flexible substrate and connected to panel pads, each obliquely extending in the first and second directions and arranged along the second direction, an alignment pad spaced along the second direction from output pads, and a stress relaxation pad disposed between output pads and alignment pads and electrically connected from panel pads.

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; trenches penetrating the second semiconductor layer and the first semiconductor region, and reaching the first semiconductor layer; gate electrodes on gate insulating films in the trenches; a first base region between the trenches; and second base regions at bottoms of the trenches. The first base region includes a lower region equal in thickness to the second base regions and an upper region on the lower region. The first base region has impurity concentration peaks of local maximum values in a thickness direction. A peak nearest an interface between the upper and lower regions is located at a position furthest from any other peak.

Abstract: A quantum dot light-emitting device includes: a first electrode; a second electrode opposite to the first electrode; an emission layer between the first electrode and the second electrode, the emission layer including quantum dots; and an inorganic layer between the emission layer and the second electrode, the inorganic layer including a metal halide.

Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor stack, a trench formed in the semiconductor stack, a current confinement layer, a first electrode and a second electrode. The semiconductor stack includes a first reflective structure, a second reflective structure, and a cavity region. The cavity is between the first reflective structure and the second reflective structure and has a first surface and a second surface opposite to the first surface. The current confinement layer is in the second reflective structure. The first electrode and the second electrode are on the first surface.

Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a substrate, a first dielectric layer disposed on the substrate, the first dielectric layer having recesses, a first conductive layer covering the first dielectric layer, and auxiliary conductive portions disposed at in the recesses and contacting the first conductive layer.

Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method includes increasing a bandgap in an outer region of a semiconductor layer by implanting ions in the outer region of the semiconductor layer and subsequently annealing the outer region of the semiconductor layer to intermix the ions with atoms within the outer region of the semiconductor layer. The semiconductor layer includes an active light emitting layer. A light outcoupling surface of the semiconductor layer has a diameter of less than 10 ?m. The outer region of the semiconductor layer extends from an outer surface of the semiconductor layer to a central region of the semiconductor layer that is shaded by a mask during the implanting of the ions.

Abstract: A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.

Abstract: A light emitting device includes an LED chip, a light-transmissible member and a light-reflecting member. The LED chip has a plurality of interconnecting side surfaces having a roughened structure and a plurality of corners. The light-transmissible member covers the side surfaces and the corners and includes a light-transmissible material layer having a breadth value W(A) of a viscosity coefficient (A) range of the light-transmissible material, which satisfies a relation of W(A)?B*D/C: where B represents a thickness of the light-transmissible material layer, represents a thickness of the LED chip measured from the first surface to the second surface, and D represents a roughness of the roughened structure. A method for manufacturing the light emitting device is also provided.

Abstract: A photoelectric conversion element and an optical sensor including the same are disclosed. The photoelectric conversion element may include a plurality of lattice stacks repeatedly stacked on top of each other on a substrate and configured to have an effective band gap. The plurality of lattice stacks may each include a first active layer and a second active layer on the first active layer. The first active layer may include a first two-dimensional material having a first band gap. The second active layer may include a second two-dimensional material having a second band gap not overlapping the first band gap. An effective band gap may be adjusted based on the first two-dimensional materials and thicknesses of the first active layer and the second active layer and a number of times of plurality of lattice stacks.

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

Abstract: Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.

Abstract: A correlated electron material device is described to comprise a conductive substrate and a layer of a correlated electron material disposed over the conductive substrate. The layer of correlated electron material may comprise a metal rich transition or other metal compound, and at least a portion of anion vacancies within the metal rich transition or other metal compound are occupied by an electron back-donating extrinsic ligand for the metal rich transition or other metal compound. Under certain conditions, the electron back-donating extrinsic ligand occupying anion vacancies may be activated so as to impart particular switching characteristics in the correlated electron material device.

Abstract: A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.