Patents Examined by Nitin C. Patel
  • Patent number: 7822968
    Abstract: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: October 26, 2010
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 7822964
    Abstract: A method for booting a computer is provided. The computer includes a booting apparatus. The method includes the steps of: powering on the booting apparatus; generating a selection signal that indicates whether a first firmware or a second firmware is to be read; acquiring the selected firmware according to the selection signal; running the acquired firmware to power on and initialize a CPU and chipsets of the computer; indicating the CPU a data path of a corresponding OS according to the acquired firmware; loading the corresponding OS; receiving commands sent by the loaded OS; and indicating the CPU to execute the commands according to the acquired firmware. A related booting apparatus is also provided.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: October 26, 2010
    Assignees: Hong Fu Jin Precision Industry (Shen Zhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Kim-Yeung Sip
  • Patent number: 7809968
    Abstract: A method for managing sleep modes in an ecosystem of components, the method includes: receiving an inactivity signal from at least one component in the ecosystem of components, the inactivity signal indicating that a predefined period of inactivity has been exceeded for that component; sending a sleep command to one or more components in the ecosystem in response to the inactivity signal, thereby establishing a sleep mode in the one or more components; subsequent to establishing the sleep mode, detecting activity in one or more of the one or more components through an awake signal received therefrom; sending an awake message to the one or more components in response to the awake signal, thereby terminating the sleep mode in the one or more components; wherein the sleep mode shuts off defined non-essential features within the one or more components, while maintaining defined essential processing tasks associated with of the one or more components placed into the sleep mode.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventor: Christopher K. Karstens
  • Patent number: 7809973
    Abstract: A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: October 5, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ronald H. Sartore, Timothy J. Williams
  • Patent number: 7809966
    Abstract: An information processing apparatus includes a communication device configured to communicate with a client apparatus via a network, an application system device configured to implement a previously installed application function, and a power controller configured to, if the communication device receives a request for starting a communication performed by the application system device from the client apparatus when the application system device is in a low power consumption state, restore the application system device from the low power consumption state to a normal power consumption state.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: October 5, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Eiji Imao
  • Patent number: 7802118
    Abstract: An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: September 21, 2010
    Assignee: Nvidia Corporation
    Inventors: Karim M. Abdalla, Robert J. Hasslen, III
  • Patent number: 7797561
    Abstract: An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is included in a processing pipeline having a plurality of functional blocks. Each functional block from the plurality is configured to receive a clock signal from a clock signal generator. A status of the functional block is determined based on the activity-level. The clock signal to at least a portion of the functional block is disabled when the status is an inactive status.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: September 14, 2010
    Assignee: Nvidia Corporation
    Inventors: Karim M. Abdalla, Robert J. Hasslen, III
  • Patent number: 7793130
    Abstract: System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: September 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsien Yang, Chung-Hsing Wang, Lee-Chung Lu, Chun-Hui Tai, Cliff Hou
  • Patent number: 7793090
    Abstract: In one embodiment, the present invention includes a method for executing a first code portion of a pre-boot environment from a first non-volatile memory, authenticating a trusted hypervisor in the first non-volatile memory using the first code portion, executing the trusted hypervisor if the trusted hypervisor is authenticated, and authenticating a basic input/output system (BIOS) present in a second non-volatile memory with the trusted hypervisor and transferring control from the trusted hypervisor to the BIOS if the BIOS is authenticated. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Mallik Bulusu, Michael A. Rothman, Robert C. Swanson
  • Patent number: 7793124
    Abstract: A power sourcing equipment (PSE) device is disclosed that includes an interface adapted to communicate with a powered device via wire pairs of a cable, a power supply circuit adapted to provide power to the interface, and device detection logic to detect the powered device coupled to the interface. The PSE device further includes power classification logic coupled to the interface and adapted to provide a power classification signal to the powered device. The power classification signal includes a first power classification signal and a second power classification signal to identify a power classification associated with the powered device. The power classification logic monitors the interface to detect a device classification response from the powered device and determines the power classification associated with the powered device based on the device classification response.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: September 7, 2010
    Assignee: Silicon Laboratories, Inc.
    Inventors: D. Matthew Landry, Russell J. Apfel
  • Patent number: 7793131
    Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 7, 2010
    Assignee: LG Electronics Inc.
    Inventors: Hyung Sun Kim, Kang Soo Seo, Byung Jin Kim, Soung Hyun Um
  • Patent number: 7793126
    Abstract: Aspects of the subject matter described herein relate to using priorities and power usage to allocate power budget to devices. In aspects, a console that maintains power usage, priorities, and other power data regarding a set of devices may receive a notification that a device has exceeded its budgeted power. In response, using priorities and power usage associated with the devices, the console determines one or more devices to instruct to use less power. A device that exceeded its budgeted power may be instructed to operate at a lower power level or another device (e.g., a lower priority device that is underutilizing its budgeted power) may be instructed to reduce its power to remain below a power budget for the set of devices.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: September 7, 2010
    Assignee: Microsoft Corporation
    Inventors: Sean Nicholas McGrane, John M. Parchem
  • Patent number: 7793123
    Abstract: A redundant power supply system aims to balance power supply among main power units and stationary power units to achieve optimum output quality for the main power units and stationary power units, and also prevent interruption of power supply resulting from any main power units or stationary power units. It includes a power integration control unit. The power integration control unit and the main power units and stationary power units are bridged respectively by a power balance unit which functions in a load power balance mode such that the power integration control unit outputs a total output power in power ON and standby conditions, and each power supply device delivers actual output power according to the load ratio of the power supply device.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 7, 2010
    Assignee: Zippy Technology Corp.
    Inventor: Tsung-Chun Chen
  • Patent number: 7793120
    Abstract: Aspects of the subject matter described herein relate to a data structure for budgeting power for multiple devices. In aspects, devices are allotted a power budget. The devices are each capable of operating at one or more power levels. A console queries the devices to obtain the power capabilities of the devices. The console stores the power capabilities in a data structure. The data structure together with the power budget may then be used to instruct each device to operate at a particular power level. The data structure includes fields for storing power levels for the devices as well as fields that associate the power levels with the devices. In addition, the data structure includes a group field that associates the devices with the power budget.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: September 7, 2010
    Assignee: Microsoft Corporation
    Inventors: Sean Nicholas McGrane, John M. Parchem, Stephen Roland Berard
  • Patent number: 7788511
    Abstract: An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention uses a feature in current DSPs with the capability of delaying ISR processing on wake from IDLE. Using this mechanism it is possible to determine the time before IDLE, the time immediately following CPU wakeup, and then run the wakeup ISR. The delta time can be accumulated and compared to total time to determine true CPU load.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Scott Paul Gary
  • Patent number: 7783876
    Abstract: A system that comprises a first electronic device comprising a non-volatile memory. The system also comprises another electronic device in communication with the first electronic device and comprising a second non-volatile memory. The system further comprises a control logic coupled to the first and second electronic devices. Each of the non-volatile memories stores electrical characteristics associated with a corresponding electronic device. Prior to booting up the first or second electronic device, the control logic obtains and compares at least some of the electrical characteristics and disables the communication as a result of the comparison.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: August 24, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul R. Culley, Kevin B. Leigh
  • Patent number: 7779289
    Abstract: A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 17, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: William Orlando, Stéphan Courcambeck
  • Patent number: 7774633
    Abstract: Cycling power in a computer to clear hang-up conditions may include disabling low voltage DC signals between an output of a standby DC power supply and standby-powered circuits in response to a power cycle request. In response to a disable signal, a power cycle module (PCM) may disable standby power being supplied to standby circuits in a computer, server, or router, for example. In addition, the PCM may disable power to main circuits by, for example, generating logic-level control signals to the power supply, or by opening a series-connected switch through which main current flows. In response to a re-enable signal, the PCM may re-enable the supply of standby and/or main power to a computer.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: August 10, 2010
    Assignee: Google Inc.
    Inventors: Kenneth L. Harrenstien, Ross Biro
  • Patent number: 7770048
    Abstract: An apparatus is disclosed. The apparatus comprises a device and a counter system coupled thereto. The counter system provides an indication of a number of times the device is inserted into a slot. Through the use of the device disclosed above, a history and a number of insertions of a particular device within a system can be known and therefore it can be determined if the integrity of the device is threatened.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Slavek P. Aksamit, David D. Chudy, Cristian Medina
  • Patent number: 7769991
    Abstract: There is provided a method and apparatus for executing an anti_virus application on a mobile communications device. A memory card for coupled to a mobile communications device, and a boot sequence is initiated on the mobile communications device. Prior to completion of the boot sequence, a Symbian recognizer is loaded to the communications device from the memory card. The loaded Symbian recognizer is executed on the mobile communications device to automatically execute an anti-virus application, the anti-virus application also being stored on the memory card.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: August 3, 2010
    Assignee: F-Secure Oyj
    Inventor: Jarno Niemelä