Abstract: It is disclosed an intelligent power monitoring unit (2) for the monitoring of a power supply (1), which comprises a power input (24) for the input of electrical power, a power output (25) for the output of electrical power, a power line connecting the power input (24) to the power output (25), a first EMI/RFI filter (21) for the reduction of electromagnetic noise on the power line, monitoring means for monitoring parameters of the electrical power on the power line and/or for monitoring parameters of the first EMI/RFI filter (21), a data processing unit (29) for receiving and processing signals from the monitoring means and for issuing control signals basing on these signals, and a data communication bus for exchanging data between the data processing unit (29) and a device (51) external to the monitoring unit (2). The invention relates as well to a power supply (1) with such an intelligent power monitoring unit (2).

Abstract: System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

Abstract: A power supply unit is arranged between a CPU and a power supply device for supplying power to the CPU. Information necessary in proceeding with a program is evacuated from the CPU to an information holding unit. When a power shutdown factor is generated, a power supply control unit outputs a shutdown request signal to the CPU. The CPU, upon receiving the shutdown request signal, activates a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after the evacuation is completed. Upon receiving the evacuation completed signal, the power supply control unit outputs a power shutdown control signal to the power supply unit. Upon receiving the power shutdown control signal from the power supply control unit, the power supply unit shuts down power supply to the CPU.

Abstract: The invention is directed towards minimizing power consumption in computer systems. One embodiment of the invention is a power management system that is used for a computer system that has at least one device and one power domain. This embodiment uses two different power managers to manage the power consumption of the device and the power domain. Specifically, this embodiment has (1) a first power manager that determines when to change power state of the device, and (2) a second power manager that determines when to change power state of the power domain. Each of these power managers decides to change the power state of its corresponding device or domain based on information from several different sources. These sources can include power-management clients and power managers of related domains or devices.

Abstract: A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Abstract: Herein disclosed is a method for controlling a semiconductor integrated circuit having plural domains, the method including controlling plural power supplies which supply power to the plural domains, controlling an asynchronous bridge section being provided between each of the domains, receiving and transmitting data for dynamically changing a power supply voltage of at least one of the domains, wherein, when a power supply voltage of one of the domains is substantially equal to a power supply voltage of the other domains, switching the power supply paths so as to supply the power supply voltage from one power supply to at least two of the domains, and switching the data paths so as to receive and transmit data between the at least two of the domains by bypassing the asynchronous bridge section.

Abstract: A system-on-chip may include a hard-macro block, a deepstop control logic circuit, and/or a multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit. The deepstop control logic circuit may be configured to transfer data to the hard-macro block from the multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit during a normal mode. The deepstop control logic circuit may be configured to latch the data output from the MTCMOS logic circuit upon an entry into a deepstop mode and interrupt a power supply to the hard-macro block during the deepstop mode.

Abstract: A power distribution system comprises an input power line configured to supply power produced by a power source, one or more power distribution components operatively connected to receive power supplied by the power source, one or more intelligent system resources, and a power management component. Each power distribution component has one or more power outputs for distributing power along a power line connected thereto and is configured to modulate a carrier signal containing identification data along the power line connected to each output. Each system resource is operatively connected to receive power distributed by at least one of the one or more power distribution components. Each system resource is configured to receive and demodulate the carrier signal modulated by each power distribution component from which it receives power, generate a list of each power distribution component from which it receives power, and pass the list to a system bus.

Abstract: A power control apparatus for automatically turning on and off a motherboard, the power control apparatus includes a power supply supplying electric power to the motherboard periodically, a control circuit including a first switch element, a second switch element, a first capacitor, a second capacitor, a first resistor, and a second resistor. When the power supply is powered up, the second capacitor is charged, the second switch element is turned on, a second terminal of the second switch element outputs a low level signal to power up the motherboard. When the motherboard is powered up, the first capacitor is charged, the first switch element is turned on, the second switch element is turned off, the second terminal of the second switch element outputs a high level signal. The motherboard is powered off when the power supply is powered off.

Abstract: A configuration of a media drive apparatus is stored as a plurality of configuration settings in a non volatile memory of a media drive apparatus. A removable storage medium is identified as a reconfiguration medium, and data is read from the removable storage medium, where the data includes an identifier of one configuration setting of the plurality of configuration settings and a value for the one configuration setting. The one configuration setting is updated with the value read from the removable storage medium.

Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.

Abstract: Methods and apparatus to simplify configuration calculation and management of a processor system are disclosed. An example disclosed method reads system configuration data from registers of a processing system, caches the system configuration data in an allocated memory, and calculates new system configuration data for the processing system by operating on cached data. Other embodiments are also disclosed and claimed.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: A computer implemented method, apparatus, and computer program product for booting a computer using a boot list. A determination is made as to whether a boot list is present in a non-volatile memory of the computer. The boot list is a set of paths, in which each path in the boot list is a path of a storage device. If the boot list is not present, a search is performed for the boot list in a reserved area of each storage device in a set of storage devices. When the boot list is found in the reserved area of a storage device in the set of storage devices, the boot list is copied from the reserved area of the storage device in the set of storage devices to form a copied boot list. The copied boot list is stored in the non-volatile memory to form a stored boot list. The computer is booted using the stored boot list in the non-volatile memory.

Abstract: A user interface is visibly displayed on a display device operatively connected to a first computer. The user interface enables an end user to enter at least one energy management rule for each of a plurality of electrical loads at a location, each rule including a command to be transmitted to the electrical load associated with the rule if a condition is met. The energy management rules for each of the plurality of electrical loads are received by a second computer. An energy management profile containing the energy management rules for each of the plurality of electrical loads at the location is created and stored using a second computer. The energy management profile is activated using the second computer. For each of the energy management rules where the condition has been met, the command associated with the rule is transmitted to the electrical load associated with the rule.

Abstract: A static pulse bus circuit and method having dynamic power supply rail selection reduces static and dynamic power consumption over that of static pulse bus designs with fixed power supply rail voltages. Every other (even) bus repeater is operated with a selectable power supply rail voltage that is selected in conformity with a state of the input signal of the bus repeater. The odd bus repeaters are operated from the lower of the selectable power supply voltages supplied to the even repeaters. The odd bus repeaters may also be operated from a selectable power supply rail voltage opposite the selectable-voltage power supply rail provided to the even bus repeaters, in which case the opposing rail of the even bus repeaters is set to the higher of the voltages selectable in the odd bus repeaters.

Abstract: Systems and methods for providing smart power management to one or more external interfaces of an information handling system that is capable of acting as a host for charging and/or otherwise powering one or more external devices via external interface/s that have both data exchange and power transfer capability, such as USB or Firewire interfaces. A host-based power source may be provided that is capable of managing power when a host information handling system is in inactive, and a user-based methodology may be implemented to selectively provide power to one or more external interfaces of a host information handling system based on user need or desire for access to external interface power, even when the host information handling system is inactive.

Abstract: A method, performed by a power sourcing apparatus is provided. The method includes (a) providing an electronic signal to a powered device (PD) over a wire through a circuit device, the circuit device permitting current to flow at pre-determined frequencies, the pre-determined frequencies forming a first set of frequency components, (b) sensing the electronic signal over the wire to detect frequency components present in the electronic signal, the detected frequency components forming a second set of frequency components, and (c) classifying the electronic signal into one of a plurality of classes according to a pattern of frequency components present in the first and second sets. Apparatus for use in conjunction with the method are also provided.