Abstract: A plurality of platforms may be defined in a distributed system. Each of the platforms may include a processor and a chipset from a common source on a single motherboard. Extensible firmware interface drivers are provided for the processors and the chipsets. Each of the platforms may be defined pursuant to a system definition model where the system definition model defines the firmware for each of the platforms. As a result, any of the platforms can be updateable from a common source, such as an Internet web site.

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller. Each nibble has at least two start bits whose states collectively represent both a function and/or destination.

Abstract: A basic input/output system may be stored on two different memories coupled to active management technology firmware and a trusted platform module. The trusted platform module ensures that access to the correct memory. One of the memories is selected to store an update of the basic input/output system.

Abstract: A system and method of managing power consumption of communication interfaces and attached devices is disclosed. In one form of the disclosure, a communication module can include a communication interface operable to receive link utilization information of a plurality of communication channels of the communication interface. The communication module can also include a processor operable to determine a percent utilization of the plurality of communication channels using the link utilization information. The processor can also be operable to initiate issuing a power management request of at least one of the plurality of communication channels in response to comparing the percentage of link utilization to a threshold level.

Abstract: Precise timing information produced by a block average module may be provided to signal processing circuitry. A sample period value generator may produce samples of the input data period values. A progressive block averaging computation may be applied to the generated input data period value samples. The output of the progressive block averaging computation may be used as the precise input sample rate information. The precise input sample rate information may in turn drive a signal processing application. The precision of the clock information may be increased with an increase in startup overhead.

Abstract: A method, system and program are provided for determining if a system clock has been reset backwards in time by using a randomly generated set of bytes (such as a randomly generated or type 4 UUID) as a time epoch. By generating a time epoch at boot time and whenever the system clock is set back in time, an application can compare the time epoch value at an earlier point in its execution, with the current time epoch. If the time epoch values are different, the application will know that the system clock has been set back in time.

Abstract: A power supply device includes a first power-supply unit to input external power and to output first power supplying a predetermined constant voltage to a load, a second power-supply unit to accumulate charge and to output second power to the load in parallel with the first power being supplied from the first power-supply unit, and a controller to output a control signal to prevent the second power-supply unit from supplying power in case of a current increase due to a dynamic load change, and to cause the first power-supply unit to supply power for the dynamic current increase. The first power-supply unit supplies power having a current value smaller than a predetermined maximum current of the first power-supply unit. The second power-supply unit supplies power for a shortfall current exceeding the predetermined maximum current of the first power-supply unit.

Abstract: A hard disk drive (HDD) self-test system comprises a basic input/output system (BIOS) configured to automatically invoke a self-test of an HDD based on a predetermined schedule.

Abstract: A machine learning technique is used to improve dynamic prediction of processor utilization for multi-threaded user-level applications in a dynamic run-time environment based on processor utilization history. Processor supply voltage and processor clock frequency may be dynamically scaled based on the predicted processor utilization in order to reduce processor power consumption.

Abstract: A portable device comprise non-volatile storage. The non-volatile storage comprises a basic input/output system (BIOS) setting. The BIOS setting is applied from the portable device onto a system to which the portable device can be coupled.

Abstract: An apparatus and method for controlling the power supplied to a fixing unit are provided. The apparatus includes a voltage detector detecting a voltage of input power supplied to heat at least one heating lamp, a synch signal generator generating a synch signal in response to the detected voltage, a switching unit switching a supply path of the input power to be applied to the at least one heating lamp, and a controller having table information of temporal duty level values of the input power that is initially supplied, and outputting a control signal for controlling a switching operation of the switching unit using the generated synch signal and the table information, wherein the switching unit performs the switching operation corresponding to the control signal.

Abstract: A CPU reads a clear pattern held in a register in a watchdog timer when a system is booted up or reset, thereby determining whether or not the boot-up or the reset is a reset performed by the system or a reset due to runaway of a program to be executed and performing a process for booting up the system so as not to restart the task in which the runaway has occurred.

Abstract: Flattening total current consumption of system having processing core and power supply input by current sensing within system at power supply input and controlling system current consumption such that system current is reduced if over reference current threshold, and increased if below reference current threshold. Inject additional current through digital injections cells working higher frequencies, by increasing switching activity, by increasing voltage supply to core, and by increasing operating frequency of processor core. Feedback signal indicates current consumption of system. Current consumption similarly decreased. Current sensed by mirroring input current inline with power supply input and compensating for voltage drop introduced by mirroring using opposing field effect transistors and maintaining outputs at same voltage through feedback control loop. Processor core may be general purpose processor core or cryptographic processor core. System may be system-on-chip or system-on-package.

Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.

Abstract: A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

Abstract: Modules are started-up for a computing system based on start-up data. Start-up data can, for example, include a dependency-matrix indicating start-up dependencies of various modules. Start-up sequences can be determined based on the start-up data and a start-up sequence can be subsequently selected based on one or more criteria. The selected start-up sequence need not include all modules, yet it can list most modules that are likely to be used in or by a computing system. In addition, software (or application) start-up can be controlled based on various criteria. As a result, software start-up is performed more efficiently and more control over system start-up is exercised.

Abstract: An apparatus and method for compensating digital input delay in an intelligent electronic device is provided. A method is provided which provides for accurate SER data recording while facilitating the reduction of processing burden on the IED and optimization of system performance during the processing of SER data flow. An apparatus is further provided which generally includes a time delay element coupled to a sequential events recorder for compensating for delay in communication of a data signal such that the sequential events recorder records a compensated time for a select event based on the clock and the time delay. An apparatus is provided which includes an edge detection element for detecting either a rising or falling edge from the data signal.

Abstract: A pin strap setting override system comprises logic configured to determine whether a pin strap setting for at least one feature of an integrated circuit (IC) is set to enable, the logic further configured to automatically override the enable pin strap setting if a flag stored in a memory indicates a disable setting for the at least one feature.

Abstract: One embodiment is a computer device that uses a timer to limit a quantity of changes to different power states that are performed on a processor in the computer device during a predetermined time period. The power states changes each have different operating frequencies for the processor.

Abstract: A clamping apparatus, for use with an actuator, has a housing with a guide track mounted on or formed in the housing. A roller or cam operably engages with the guide track such that the cam can be moved and positioned along the guide track by way of the actuator. At least one pivoting arm is pivotally mounted on the housing adjacent to and spaced from the guide track. Each pivoting arm has an elongate slot adjacent to the shoulder. The elongate slot has two arcuate surfaces positioned parallel to each other and has two end surfaces joining the arcuate surfaces to define a closed loop surface. The cam is positioned within the elongate slot of each pivoting arm to pivot each pivoting arm between a clamped position and a released position as the cam is moved along the guide track and driven against the arcuate surfaces of each pivoting arm.