Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: A configurator is provided with the ability to present a customer with information regarding desirable configuration bundles that are based upon specific intended use and to enable a customer to configure a system based upon the specific intended use. Additionally, based upon an indicated specific intended use, an information handling system manufacturer can optimize the configuration of the information handling system.

Abstract: A system for multi-profile boot selection of an embedded device and method therefor are described. The system comprises a storage device reader, a processing device, and a memory. The processing device communicates with the storage device reader and the memory stores instructions including a boot controller which, when executed by the processing device, interacts with the storage device reader and automatically generates a default boot configuration file based on determining a failure from interaction with the storage device reader.

Abstract: The subject application is directed to a method and system for notifying an administrator when a user of a document processing device requests a change in the configuration of the device. A user accesses the device via a user interface, requesting alteration of the device configuration. The user then provides identification information and an authentication server determines whether the identified user is authorized to make the configuration change. Access is denied to unverified or unauthorized users attempting to change the configuration of the device. When the user is verified, but not authorized to make the requested change, the authentication server rejects the request and notifies the administrator of the attempt. When the user is both verified and authorized to make a change, the device configuration is altered, conforming to the requested configuration, and a notice is transmitted to the administrator containing information about the change in configuration.

Abstract: The power supply is effectively controlled in a semiconductor integrated circuit device having a multi domain structure so as to reduce the power consumption. When an interrupt signal is inputted, the system controller makes an instruction of wakeup to the corresponding switch control unit. At this moment, the system controller controls power supply so as to be supplied sequentially from the core power source area belonging to the lower hierarchical level dependent on the core power source area to which power is supplied. The system controller outputs the power supply switch-on request signal to the switch control unit. The switch control unit turns ON the power supply switch and sends the power-on completion signal back to the system controller. Similarly, the system controller supplies power sequentially to core power source areas in the dependency relation one after another from the lower hierarchy to the upper hierarchy.

Abstract: An embodiment of the invention is meant to prevent/allow microcode updates after an operating system is booted on a platform. A processor includes a lock directive that, when set, prevents microcode updates to occur after the operating system has been booted. In an embodiment, the lock directive is read during boot of the processor. A lock indicator is then written to an accessible location so that an attempt to patch, or update, microcode after the operating system has booted will be prohibited if the lock indicator indicates that microcode patch updates are not allowed. Other embodiments are also described and claimed.

Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.

Abstract: A system abstraction layer enables selection from among at least two different processor abstraction layer components. By allowing the selection from a plurality of compressed components, better system adaptability may be achieved. For example, updates may be provided so that it is not necessary to update the entire basic input/output system each time a component of the processor abstraction layer needs to be updated. In addition, a variety of different platforms may be supported by one basic input/output system having a plurality of selectable processor abstraction layer component images.

Abstract: A high security palisade fence is formed from a plurality of vertical posts, each of which is characterized by a pair of flange sections which are joined by an intermediate flat web section having a double-walled structure. One or more cable passageways are formed in each post. Each adjacent pair of posts is interconnected by a plurality of parallel rails. Each rail is formed with an internal tray, within which a strengthening cable may extend. Vertical pickets are attached to the rails. The pickets are preferably characterized by a W-shaped profile, and preferably include longitudinal strengthening ribs. Each picket has a flat attachment surface in which a plurality of subsurface recesses are formed.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network.

Abstract: When a plurality of electric devices is charged, each electric device is charged by priorities. The data processing apparatus related to the present invention comprises; a first data processing unit which comprises a first memory, a first data control section and a first battery; a second data processing unit which comprises a second memory, a second data control section and a second battery. The first data processing unit and the second data processing unit can be mechanically attached to and removed from each other.

Abstract: A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number.

Abstract: A computer host with bus interface includes a power supply and a motherboard. The power supply has a main power system and a standby power system. The DC power outputted by the standby power system is used to drive a power on/off unit, which is used for outputting a computer operating signal and a computer shutdown signal. The motherboard has a logic operation circuit and a data transmission port electrically connected to inner electronic device. A bus interface is installed on the computer host and the bus interface has a power transmission terminal and a data transmission terminal. The data transmission terminal is electrically connected with the data transmission port of the motherboard, and the power transmission terminal is electrically connected to the standby power system such that the bus interface can receive the DC power from the standby power system when the computer host is under operation or shutdown.

Abstract: A method is provided of determining total electric power consumption of a managed IT network including network devices having a management-addressable address. An autodiscovery tool is run to discover the network devices of the managed IT network. Management requests are directed to the management-addressable addresses of the network devices to obtain the electric power consumption values of the network devices. The electric power consumption values returned by the network devices are centrally collected, and the total electric power consumption of the managed IT network is calculated by adding the electric power consumption values of the network devices.

Abstract: A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Abstract: A mode selector is operable to select either a first display mode or a second display mode. A controller is operable to cause each of a display and an operating section configured to perform a prescribed operation to be placed in either a first power mode in which a first level of power supplied from a power supply is consumed or a second power mode in which a second level of power supplied from the power supply which is lower than the first level is consumed, and operable to cause the display to display a first image in a case where the first display mode is selected, and to display a second image different from the first image in a case where the second display mode is selected. The controller is operable to cause the operating section to transit from the first power mode to the second power mode when the operating section does not perform the prescribed operation for a first time period.

Abstract: The invention relates to a power supply device that has a plurality of power supply components. The power supply components are provided with one communication interface each and are linked with a common analysis and control unit via the communication interface and a communication channel. The analysis and control unit controls a load moment of the power supply components. The analysis and control unit feeds control signals to the power supply based upon the mode of operation if the power supply is switched over or reprogrammed.

Abstract: An apparatus, system, and method are disclosed for booting a Logical Partition using an external storage device. The method creates a virtual SCSI device assigned to a first logical partition (“LPAR”) of a first computer using a virtual I/O server by mapping a LUN of a storage volume to a SCSI ID. The storage volume is located external to the first computer and the first LPAR is configured to share one or more physical processors and one or more physical I/O devices of the first computer with a plurality of LPARs. The method receives a boot request to boot the first LPAR. The boot request identifies the storage volume as a boot device using the SCSI ID of the virtual SCSI device. The method retrieves boot data from the storage volume using a SCSI driver of the first LPAR and boots the first LPAR using the boot data.

Abstract: An apparatus having a power saving mode function and method controlling the power saving mode thereof is provided. A USB connector provides a communication interface with a USB external device by use of a USB cable. A USB controller determines whether a voltage is supplied from the USB external device based on a value of the voltage input from the USB connector. A main controller enters either the power saving mode or a standby mode based on the determination of the USB controller. Accordingly, if the computer is turned off, the apparatus enters the power saving mode before a predetermined time passes, to thus prevent the waste of power.

Abstract: A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.