Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.
Type:
Grant
Filed:
July 10, 2007
Date of Patent:
January 18, 2011
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Hyuk-Jun Sung, Chan-Yong Kim, Jong-Pil Cho
Abstract: A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
Type:
Grant
Filed:
June 26, 2007
Date of Patent:
January 18, 2011
Assignee:
International Business Machines Corporation
Abstract: An improved portable media device and methods for operating a media device are disclosed. According to one aspect, the portable media device has the capability to store media device status information in persistent memory before powering down. Thereafter, when the portable media device is again powered up, the stored media player status information can be retrieved and utilized. According to another aspect, the portable media device can form and/or traverse a media asset playlist in an efficient manner.
Type:
Grant
Filed:
March 3, 2009
Date of Patent:
January 4, 2011
Assignee:
Apple Inc.
Inventors:
Muthya K. Girish, Aram Lindahl, Morgan Woodson
Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.
Type:
Grant
Filed:
June 16, 2008
Date of Patent:
January 4, 2011
Assignee:
International Business Machines Corporation
Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.
Abstract: Systems and methods are provided for performing maintenance on a multiple-slot device having multiple adapters in a computer system including a peripheral interface having a plurality of device connection slots. The invention includes determining that a selected slot on the peripheral interface is associated with an adapter of a multiple-slot device, identifying a further slot associated with the multiple-slot device based on the selected slot, and providing power to, or removing power from, the selected slot and the identified further slot. Numerous other aspects are provided.
Type:
Grant
Filed:
June 26, 2007
Date of Patent:
December 28, 2010
Assignee:
International Business Machines Corporation
Abstract: An improved portable media device and methods for operating a media device are disclosed. According to one aspect, the portable media device has the capability to store media device status information in persistent memory before powering down. Thereafter, when the portable media device is again powered up, the stored media player status information can be retrieved and utilized. According to another aspect, the portable media device can form and/or traverse a media asset playlist in an efficient manner.
Type:
Grant
Filed:
March 18, 2009
Date of Patent:
December 21, 2010
Assignee:
Apple Inc.
Inventors:
Muthya K. Girish, Aram Lindahl, Morgan Woodson
Abstract: A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.
Abstract: A method for controlling power supply in a computer system includes receiving a control command, and providing power through an interface of the computer system when the computer system is operating in a low power consumption mode.
Abstract: A method for changing a booting source when a first operating system is being executed is disclosed. The method is utilized in a computer system having a first storage device storing the first operating system and a second storage device storing a second operating system. The method includes: receiving a signal from the second storage device; detecting whether the second storage device is a target device; setting the second storage device as a booting device; rebooting; and executing the second operating system from the second storage device.
Abstract: A data processing system refreshes a display at a first frequency when operating in a first power mode. The data processing system refreshes the display at a second frequency when operating in a second mode. The first frequency is higher than the second frequency, and the second power mode is configured to consume less power than the first power mode.
Abstract: A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a full frequency data type, a half frequency data type, or a crossed data type. Once determined, the logic analyzer reconstructs the debug data such that debug condition-matching logic may process the reconstructed data in a full frequency domain. For half frequency data types, the logic analyzer adds masked data values to the data in order to reconstruct the data into to the full frequency domain before processing the data. For crossed data types, the logic analyzer reconstructs the data into its original format before processing the data in a full frequency domain.
Type:
Grant
Filed:
June 4, 2007
Date of Patent:
November 30, 2010
Assignee:
International Business Machines Corporation
Inventors:
Michael Joseph Genden, John Fred Spannaus
Abstract: A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.
Abstract: A management technique provides for management of power supply modules. In multiple computer equipment, in response to a load state, if an operation system issues a command that changes a processor state of a processor to a sleep state, a management module is notified through a management network MI that the processor state has changed. The management module holds a system information, and performs the steps of: updating system information because the processor state has changed; from this system information, calculating the power consumption required for the multiple computer equipment; determining the number of required AC-DC power supply modules to be operated; and changing the number of operating AC-DC power supply modules by use of a control interface PA.
Abstract: Disclosed is a method and apparatus for sharing sensitive data. A trusted operating system is configured to securely execute boot instructions for one or more hardware component. A virtual operating system in communication with the trusted operating system is configured with one or more security policies defining access rights associated with the one or more hardware component.
Type:
Grant
Filed:
May 31, 2007
Date of Patent:
November 23, 2010
Inventors:
Zachary Nathaniel Joseph Peterson, Adam Bradley Stubblefield, Stephen C. Bono, Matthew Daniel Green
Abstract: In a virtualization computer system, a method and system that does not exclusively allocate I/O devices, for example, storage and networking devices, to a commodity operating system (COS) when mainly used for booting the virtualization system. Those I/O devices needed by the COS are accessed via virtual machine kernel drivers, thereby giving the COS the benefits of operation derived from features in the virtual machine kernel that is provided for these I/O devices.
Abstract: This demodulator for signals transmitted by bursts of data packets and the corresponding method comprise receiving from a separate processor identifiers of bursts to be processed, filtering the signals to retrieve the bursts whose identifiers were received, processing said retrieved bursts, receiving from said separate processor timing information associated with the identifiers of bursts to be processed; and power management to drive at least some components of said demodulator between an idle state and an active state depending upon said timing information.
Abstract: Methods, systems, and computer program products are provided for making PEI phase implementation independent from DXE phase implementation in a computer system implementing the Extensible Firmware Interface standard. For example, one embodiment of the present invention uses a hand-off block to make SMBASE initialization in PEI independent form SMBASE initialization in DXE. In another embodiment of the present invention, PEI phase is entered in order to resume from an S3 standby state.
Abstract: The power supply management system is provided with an information processor and a terminal that is connected to the information processor by a communication line and a power supply line and that is controlled for power supply by the information processor. The terminal includes a monitor unit that is capable of monitoring at least any one of a signal received from the outside through the communication line and a signal detected inside by using the electric power supplied through the power supply line and a change unit that changes an internal power supply path so as to supply electric power other than the electric power supplied through the power supply line on the basis of the monitoring results of the monitor unit.
Abstract: An exemplary method of operating an electronic device comprises determining if the electronic device is in a low power mode. The exemplary method also comprises continuing normal operation if the electronic device is not in the low power mode, determining if a wake-up timer is set if the electronic device is in the low power mode, continuing normal operation in low power mode if the wake-up timer is not set, and disabling low power mode if the electronic device is in the low power mode of operation and the wake-up timer is set.