Patents Examined by Nitin C. Patel
  • Apparatus for sequentially enabling and disabling multiple powers
    Patent number: 7464275
    Abstract: Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: December 9, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae Young Lim, Han Jin Cho, Soon Il Yeo, Ig Kyun Kim, Kyoung Seon Shin, Hee Bum Jung
  • First-time startup device warranty user interface notification
    Patent number: 7461246
    Abstract: A first time startup mechanism for use with an electronic device to determine whether the device has been previously started. The first time startup mechanism determines whether device has been previously started. If the device has then been previously started, the device operates as normal. If the device has not been previously started, then the user is provided with notification as such.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: December 2, 2008
    Assignee: Nokia Corporation
    Inventor: Niall O'Donoghue
  • Skip counter for system timer
    Patent number: 7461283
    Abstract: A skip counter timing device employing a typical hardware system timer, a skip counter with a skip count register, a signal gate and a hardware system tick counter as a single sleep mode enhancing skip counter. In an exemplary embodiment, said skip counter is operatively interconnected to a legacy operating system, with said operating system being configured for said interconnection. Use of said skip counter provides the benefits of: 1) allowing CPU shutdown during device sleep modes while 2) eliminating the need for the CPU to perform fractional mathematical calculations in recalculating accurate timer settings upon factional time-slice timer interrupt firings at CPU restarts and thus 3) avoiding overloading CPU resources at said restarts and 4) eliminating incremental and cumulative inaccuracies associated with recalculating timer settings in dynamic timer-managed systems.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 2, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Vitaly Andrianov
  • System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
    Patent number: 7461286
    Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Ralph James
  • Power control of remote apparatus via network
    Patent number: 7461278
    Abstract: A power consumption control method for collectively controlling the power consumption of electronic apparatuses connected to a network is provided. When an electronic apparatus is connected to the network, a management device performs power-saving control for the electronic apparatus. When the electronic apparatus is disconnected from the network, the electronic apparatus performs the power-saving control for itself. Thus, the power consumption of the clients connected to the network can be effectively reduced.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: December 2, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoshifusa Togawa
  • Method for maximizing server utilization in a resource constrained environment
    Patent number: 7461274
    Abstract: A mechanism for controlling the hardware resources on a blade server, and thereby limiting the power consumption of the blade server is disclosed. The enforceable hardware resources that are controlled include the base frequency of the central processing unit (CPU) as well as power to individual banks of physical memory, for example dual-inline memory modules (DIMMs). The hardware resources are tuned in dependence on actual server utilization such that applications running on the blade only have the allocated hardware resources available to them. Deactivated hardware resources are powered off and are so ‘hidden’ from the operating system when they are not required. In this manner, power consumption in the entire chassis can be managed such that all server blades can be powered on and operate at higher steady-state utilization. The utilization of the powered on resources in a blade center is also improved.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventor: Aaron E. Merkin
  • Circuit and method for monitoring the status of a clock signal
    Patent number: 7454645
    Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: November 18, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventors: Gabriel M. Li, Greg J. Richmond, Sangeeta Raman
  • System and method for managing configuration data for a multi-cell computer system
    Patent number: 7451302
    Abstract: According to at least one embodiment, a method of managing configuration data for a multi-cell computer system is provided. The method comprises storing configuration data for a given multi-cell computer system to nonvolatile memory of at least one cell of the given multi-cell computer system. The method further comprises storing a corresponding identifier to the nonvolatile memory of the at least one cell that uniquely identifies the given multi-cell computer system to which the stored configuration data corresponds.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: November 11, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Scott Lynn Michaelis, Greg Albrecht, Jason Reasor
  • Method and a system for designating a user selected console device as the primary console device for a particular computer
    Patent number: 7447900
    Abstract: Methods and systems for designating a user selected console device as the primary console device for a particular computer are provided. In one embodiment, information indicating which potential primary console device associated with a particular computer is the user selected console device is received. The user selected console device is designated as the primary console device for the particular computer.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: November 4, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dong Wei, Frederick G. Kleinsorge
  • Disk drive input sequencing for staggered drive spin-up
    Patent number: 7447926
    Abstract: Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: November 4, 2008
    Assignee: EMC Corporation
    Inventors: John V. Burroughs, Stephen E. Strickland, Timothy E. Dorr
  • Method for fast activation and playing of multimedia data with non-fixed data storage media
    Patent number: 7447890
    Abstract: A method for fast activation and playing of multimedia data with a non-fixed data storage media, such as compact disk, is provided. The storage media, pre-installed with an operating system, is used to activate the computer. Then the media player connected to the computer is detected, and a device driver for the detected media player and a corresponding media playing application in the storage media are executed. The process further includes establishing a RAM disk area in the RAM of the computer for the space required by executing the operating system, device driver for the media player, and the media playing application programs.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 4, 2008
    Assignee: Mitac Technology Corp.
    Inventors: Chien-Chung Lee, Juyang Chang
  • Method and apparatus for delivering device drivers
    Patent number: 7444503
    Abstract: A method and apparatus for delivering a device driver to an operating system without user intervention. One or more operating systems (e.g., different operating system programs, different versions of one operating system) execute on a computer platform. During booting of an operating system a device is identified for which a driver is needed. The driver is requested from a service processor of the platform, which includes memory or storage for storing multiple device drivers (or multiple versions of one driver, for different operating systems). The driver is retrieved from the service processor's storage and delivered to the operating system.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: October 28, 2008
    Assignee: Sun Microsystems, Inc
    Inventors: Ashley N. Saulsbury, David J. Redman, Gregory C. Onufer, John G. Johnson
  • Dynamic voltage transitions
    Patent number: 7444524
    Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Robert Greiner, Matthew M. Ma, Kevin Dai
  • Power-state management of peripheral device by north bridge for power management of computer system
    Patent number: 7441128
    Abstract: In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: October 21, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Tony Ho, Wayne Tseng
  • Offloading the processing of a network protocol stack
    Patent number: 7441112
    Abstract: A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to include a first processing unit and the second partition to include a second processing unit. An Input/Output (I/O) operating system is booted on the first partition. A general purpose operating system is booted on the second partition. Network transactions are issued by the general purpose operating system to be performed by the I/O operating system. The network transactions are performed by the I/O operating system.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Michael A. Rothman
  • Dynamic voltage scaling system
    Patent number: 7437580
    Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: October 14, 2008
    Assignee: QUALCOMM Incorporated
    Inventors: Eric L. Henderson, Michael Drop, Tauseef Kazi
  • Infrastructure for verifying configuration and health of a multi-node computer system
    Patent number: 7434041
    Abstract: A verification infrastructure uses a verification tool with a user interface with which a user may interact to verify an application and/or its platform. The user may enter the same set of commands to verify instances of the application on different platforms. Furthermore, the verification tool is data driven in a way that allows the verification tool to be easily extended to new platforms. Finally, details of a particular configuration are stored persistently and are used by the verification tool to perform verification. Thus, much of the complex work of acquiring knowledge about the configuration and applying the knowledge to the results of various checks made for verification is performed by the verification tool and not a human user.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 7, 2008
    Assignee: Oracle International Corporation
    Inventors: Alok Kumar Srivastava, Dipak Saggi, Babak Hamadani, Sambit Mishra
  • Electronic circuit with asynchronous clocking of peripheral units
    Patent number: 7428651
    Abstract: An inventive electronic circuit includes central processing means having a clock connection and a data connection, as well as a peripheral unit having a clock connection and a data connection, the clock connection of the peripheral unit being connected to a signal output of a controllable oscillator or to an external clock input. Synchronization means having a first and a second data connection is connected, the first data connection being connected to the data connection of the peripheral unit. In addition a data bus connects the data connection of the CPU and the second data connection of the synchronization means. The clocking of the peripheral unit asynchronous to the central processing unit yields a more effective operation being better adjustable to certain parameters, such as, for example, the application and the energy of the electronic circuit available.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: September 23, 2008
    Assignee: Infineon Technologies AG
    Inventors: Astrid Elbe, Norbert Janssen, Holger Sedlak
  • Methods and apparatus to selectively power functional units
    Patent number: 7428645
    Abstract: A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: September 23, 2008
    Assignee: Marvell International, Ltd.
    Inventors: Dennis M. O'Connor, Michael W. Morrow, Lawrence T. Clark
  • Low power media player for an electronic device
    Patent number: 7426647
    Abstract: A low power media player is provided for an electronic device, such as a hand-held portable computer having capability to operate an application during a low power mode. During the low power mode, portions of hardware, software, services, and/or other components of the portable computer that are not necessary to the operation of the low power media player are suspended or otherwise deactivated. Rather than repeatedly accessing a hard disk to read media files for playback, the low power media player limits its number of access operations by reading as many media files as possible during each access operation, and then caching the read media files. When playback of the media files is to be performed, the media files are read from the cache, thereby reducing the amount of power consumption attributable to hard disk access operations.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: September 16, 2008
    Assignee: Vulcan Portals Inc.
    Inventors: Rod G. Fleck, Rex Antony Flynn, Martin J. Kee, Stephen L. Perrin