Abstract: Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a phase difference between an absolute time reference signal and a compensated generated input signal, an IRIG encoder configured to couple a present time value with the generated output signal to form an IRIG waveform, a delay difference indicator configured to provide a time interval value based on a comparison of corresponding pulse edges of the generated output signal and the IRIG waveform, and a numerical delay component configured to delay the generated output signal by the time interval value to form the compensated generated input signal used to time-align the IRIG waveform with the absolute time reference signal to form the accurate IRIG waveform.

Abstract: The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a delayed input signal, a counter adapted to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto, a circuit adapted to produce a fine timing signal based on the input signal, and a circuit adapted to combine the coarse timing signal and the fine timing signal to produce an output signal.

Abstract: An output system having an output device that performs output based on output data so that the output device performs the output after having acquired authentication. In the system, an operating state controlling unit outputs a power-save-cancel command for causing a power-saving state to be changed into an active state to a power-save switching unit after a device having an output data storing unit acquires the output data, and a transition-to-power-save command for causing the state to be changed from the active state to the power-saving state is outputted to the power-save switching unit when the output process of the output data is completed by an output process completion detecting unit.

Abstract: Methods and apparatus are provided for conveying configuration data to a programmable logic device integrated circuit. When the configuration data is loaded into configuration memory on the programmable logic device integrated circuit, the programmable logic device integrated circuit performs custom logic functions. The programmable logic device integrated circuit or an associated configuration device integrated circuit may be provided with power conversion circuitry and transceiver circuitry. The power conversion circuitry converts received radio-frequency signals into power. The power from the power conversion circuitry is provided to the transceiver, loading, and configuration memory circuitry. The transceiver circuitry is connected to an antenna that receives wirelessly-transmitted configuration data and is used to transmit confirmation messages following successful loading of the configuration data into the configuration memory.

Abstract: The invention relates to an electronic device comprising at least two power management circuits and a signal line connecting the circuits. Each of the circuits is adapted to control a power supply to at least one functional component of the electronic device. Each of the circuits is adapted to detect a condition which requires powering down functional components of said electronic device and to set the signal line to a predetermined state, in case the circuit detects a condition which requires a powering down of the electronic device. Further, each of the circuits is adapted to monitor a state of the signal line and to power down all functional components associated to it upon detection of the predetermined state of the signal line.

Abstract: A network interface comprises a medium access control (MAC) device and/or a host interface. A regulator module communicates with the MAC device and/or the host interface and provides a first voltage level during an inactive mode and a second voltage level during an active mode. A physical layer (PHY) device that communicates with the MAC device and/or the host interface and the regulator module and that includes an energy detect module that detects energy on a medium during the inactive mode and an energy save module. The energy save module starts timing a first period and the regulator module transitions the MAC device and/or the host interface to the second voltage level when the energy is detected during the inactive mode. External communication with the MAC device and/or the host interface is enabled after the first period is up.

Abstract: A circuit is provided for generating clock signals for clocking a digital signal processor (DSP) and a memory, the circuit comprising of a clock generator for receiving a first clock, generating a DSP clock signal by dividing the first clock by X, and generating a memory clock signal based on the first clock and the DSP clock signal, wherein the DSP is clocked by the DSP clock to generate a write command for writing data into the memory and to generate a read command for reading data in the memory, and data is written into the memory or read from the memory in response to the memory clock signal. A method is also provided for accessing a memory, the method comprising of receiving a first clock; generating a DSP clock signal by dividing by X the first clock; generating a memory clock signal according to the first clock and the DSP clock signal; outputting DSP data in response to the DSP clock signal; and reading data from a memory or writing the DSP data into the memory in response to the memory clock signal.

Abstract: Methods, systems, and media are disclosed for improved granularity of a response-request communication on a networked computer system. One example embodiment includes receiving the request-response communication by the networked computer system, and associating the request-response communication with a port, having a nodelay setting, from a set of ports on the networked computer system. Further, the example embodiment includes enabling, based upon the associating, the nodelay setting upon connection of the request-response communication with the port. Further still, the example embodiment includes sending, in accordance with the enabling, the request-response communication to a destination in communication with the networked computer system.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A device and method for making a peripheral device compliant with a power management standard, such as the USB standard, are described. The device includes a power management unit (PMU) and a timing unit. The PMU is coupled to a battery pack and to a processor of the peripheral device, and manages power allocated to the processor. The timing unit sends electrical signals to the input terminals of the PMU when the battery pack is connected to the peripheral device. The electrical signals activate the processor via the PMU. The timing unit sends the electrical signals before a configurable time from the time when the battery pack is connected to the peripheral device.

Abstract: Power usage of computing device components is controlled in a holistic manner. The projected total power consumption for the computing device to satisfy a power consumption policy for the device is determined. Power usage of each component of the computing device is controlled in a holistic manner—i.e., balancing the power usage of the component against the power usage of other components—so that the total power usage of the computing device falls within the projected total power consumption needed to satisfy the power consumption policy. How the user is currently utilizing the computing device may be periodically detected, based at least on a power consumption distribution of the components of the computing device. A current usage model is determined based on how the user is currently utilizing the computing device. The power usage of each component of the computing device is controlled based on the current usage model.

Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described.

Abstract: An information handling system includes a power source configured to provide a plurality of power levels to a load. At least one of the plurality of power levels corresponds to a level obtained by de-rating a capacity of the power source from a nominal design specification of the power source.

Abstract: An information handling system (IHS) employs a power fault protection circuit to protect the IHS from overvoltages which may occur on an information line from a power adapter to the IHS. The system includes a processor coupled to the protection circuit. The circuit is operative in a first mode to decouple an information line from the IHS in response to a disable command and operative in a second mode to decouple the information line from the IHS when a voltage in the information line exceeds a predetermined threshold voltage.

Abstract: A power-saving processing unit is provided which is capable of realizing proper mode switching by taking into account a power consumption as well in a shift processing and a return processing for switching an operation mode. In a power-consumption information table 170, there are recorded a power consumption (mJ) which is required for a processing for shifting into a power-saving mode, a consumed power (mW) when an operation is executed in the power-saving mode and a power consumption (mJ) which is required for a processing for returning to an ordinary mode. A time prediction section 102 refers to a timer-list management queue 201 and predicts a period of time until the power-saving mode is removed.

Abstract: A method for configuring a plasma cluster tool is disclosed. The method includes generating a key file from option specifications, the key file encapsulating configuration restrictions specifically imposed on the plasma cluster tool. The method also includes generating at least one system-wide configuration file and at least one component-level configuration file using the key file. The method additionally includes generating run-time executable objects from a database of option definition files, the at least one system-wide configuration file and the at least one component-level configuration file. Furthermore, the method includes employing the run-time executable objects to configure the plasma cluster tool.

Abstract: A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.

Abstract: An information handling system having a plurality of blade server modules (BSMs) and power supply units (PSUs) uses a module monitor board (MMB) to monitor and control a power budget of the PSUs by each individual BSM requesting authorization from the MMB in order to power ON and boot-up. A blade management controller (BMC) may communicate with the MMB over a communications bus. However, if the firmware application controlling the BMC has been corrupted the BMC it may run in a “boot block” mode and not contain the intelligence necessary to obtain power ON authorization from the MMB. A single, existing input-output (I/O) line from the MMB to the BMC may be utilized to indicate power ON authorization for the respective BSM. The MMB and BMC may be adapted for preventing the BSM from powering ON without proper authorization from the MMB and that the BMC will always power ON the BSM when enough power is available from the PSU.

Abstract: A multimedia reproducing apparatus having excellent operability and amenity. In the apparatus, a ROM contains an OS including a system program and a utility program. A control unit controls at suspend function by which data indicating the state of contents of display and contents of execution before interruption of a power supply to a CPU is stored as save data so that the power supply, after interrupted, can be resumed from the state before interruption. A main memory includes a first area for the save data to be written to when suspend is executed, and a second area for data of an external program to be written to when the external program is executed. The system program has the functions of writing the save data to the first area when suspend is executed, and writing the utility program from the ROM to the first area when suspend is not executed and the utility program is called from the external program.

Abstract: A method and apparatus for configuring a plurality of computers, each of which requires interaction with at least one resource to advance a configuration state of the computer. A request for access to a resource may be received from at least one of the computers, and a resource needed may be determined. An availability of the resource needed may be determined, and the computer instructed to interact with the resource if the resource is available. If the resource is not available, the computer may be caused to not interact with the resource.