Abstract: Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.

Abstract: A method for preventing an excess voltage from appearing at an output of a power over Ethernet controller, the method comprising: sensing that a powered device has been disconnected from a port; enabling a bypass path around a means for unidirectional current flow operatively connected to the port; and disconnecting power to the port responsive to the sensed disconnect, whereby the bypass path enables a discharge path for an output capacitor present across the port. The invention also provides for a circuit having a bypass path around a means for unidirectional current flow, the bypass path being enabled by a control circuit to prevent an excess voltage from appearing at a sensing input of the control circuit. In an exemplary embodiment the bypass path is enabled approximately simultaneously with disconnecting power from the output port.

Abstract: A system for starting up plural electronic devices includes an external controller, a power source, and four backboards. The external controller includes four output ends. Each backboard includes a power switch connected to a respective electronic device and to the power source, an onboard controller connected to the respective power switch, and first and second connectors each having four ends. Fourth, first, second and third ends of the first connector are respectively connected to first, second, third, fourth ends of the second connector. The onboard controller includes four input ends respectively connected to the four ends of the first connector, and an output end connected to the power switch. Signals output from the external controller are received as four different input signals at the four onboard controllers, the input signals corresponding to four different time delays for the onboard controllers to output signals to start up the four electronic devices.

Abstract: A first physical layer device of a first network device includes a sense circuit that senses activity on a medium and with the first physical layer device. An autonegotiation circuit attempts to establish a connection with a second physical layer device of a second network device within a first period after the sense circuit senses activity. An energy saving circuit selectively provides power to the first physical layer device based on the sensed activity and connection with the second physical layer device, and that while attempting to establish the connection resets a timer associated with the first period when the sense circuit senses activity.

Abstract: A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to store a preferred memory device voltage configuration corresponding to a preferred operating voltage of the memory device. The preferred memory device voltage configuration is readable by a host and the circuit is responsive to a command to modify the voltage to the memory device in accordance with the preferred memory device configuration. The voltage to the memory device is modified for improved performance and compatibility of the memory device with a host system.

Abstract: Methods, systems, and media are disclosed for improved granularity of a response-request communication on a networked computer system. One example embodiment includes receiving the request-response communication by the networked computer system, and associating the request-response communication with a port, having a nodelay setting, from a set of ports on the networked computer system. Further, the example embodiment includes enabling, based upon the associating, the nodelay setting upon connection of the request-response communication with the port. Further still, the example embodiment includes sending, in accordance with the enabling, the request-response communication to a destination in communication with the networked computer system.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the power and configuration management system of the computer system.

Abstract: A method and apparatus for a user to interface with a mobile computing device is disclosed.

Abstract: A method and system for notifying an administrator when a user of a document processing device, such as a multifunction peripheral device, requests a change in the configuration of the document processing device. A user accesses the document processing device via a user interface, requesting that the configuration of the device be altered. The user then provides identification information verifying the identity of the user. An authentication server then determines whether or not the identified user is authorized to make the change in the device configuration. Access is denied to unverified or unauthorized users attempting to change the configuration of the document processing device. In the event that the user is verified, but not authorized to make the requested change, the authentication server rejects the requested change and notifies the administrator of the attempt to change the configuration.

Abstract: A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to synchronize their occupancy. In addition, the traffic card includes a clock control logic, including a phase adjuster, to adjust the phase of clock signals driving the two ingress FIFOs to avoid an underflow or overflow.

Abstract: A startup system using a boot code includes an external memory storing a boot code, a buffer connected to an external memory for storing the boot code transferred from the external memory, a DMA controller for commanding transfer of the boot code from the external memory to the buffer, and a mapping circuit connected to the buffer for mapping the boot code stored in the buffer onto a CPU. Accordingly, a flash ROM for storing the boot code may be eliminated, thereby reducing system cost.

Abstract: A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device and a peripheral device in the system, the transactions being transmitted between the peripheral device and the chipset device according to a flow control protocol to allow the chipset device to keep track of the transactions, and causing a processor in the system to exit from a power state if a plurality of coherent transactions pending in a buffer of the chipset device exceeds a first threshold. Other embodiments are described and claimed.

Abstract: A first vendor generates one or more files corresponding to an integrated circuit having one or more registers. A content of the files is structured for at least one of: (i) incorporation into a boot code sequence; or (ii) access by the boot code sequence during execution. The boot code sequence is configured to initialize the registers responsive to the content during execution. The first vendor transmits the files to at least one of: (i) a second vendor that develops the boot code sequence; or (ii) a manufacturer of a system that includes the integrated circuit and the boot code sequence. A computer accessible medium comprises instructions which, when executed, generate the files described above and/or comprises the files. A method may include receiving, from the first vendor, the files described above. The content of the files is incorporated into the boot code sequence.

Abstract: A monitor for controlling power-on and power-off of a host computer includes a switch device, a monitoring device and a transmission device. The host computer has a processing device. The switch device is used for changing a status thereof in response to an external force applied thereto. The monitoring device is electrically connected to the switch device for monitoring the change of the status of the switch device, and determines if a power management event is activated by the change of the status of the switch status. The transmission device is electrically connected to the monitoring device, and transmits a power management signal to the host computer according to the determination that the change of the status of the switching device activates a power management event, such that the processing device performs a startup power-on or a power-off operation on the host computer.

Abstract: A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T2. T1 is then subtracted from T2 to obtain a time difference DT which is multiplied by ((1?1/DF)?1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T3. When a test T3 minus T2 is not less than DD, then T1 is set to T3. Then, the procedure is repeated for a next group of instructions.

Abstract: The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

Abstract: A digital wake-up signal is generated from an analog switch on a printed circuit board in which a ground trace and multiple conductive switch traces are bridged by a moveable contactor responsive to movement of an actuator. A resistor network is coupled to the switch traces and alternatingly connects the switch traces to two outputs to generate distinct analog voltage outputs. A logic gate determines when both outputs are at the same voltage corresponding to the contactor engaged between two adjacent switch traces and generates a wake-up command signal.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A docking station for a wireless mouse includes an output for communicating with a computer and a mouse detector for detecting when the mouse is docked in the docking station. The docking station is configured to transmit a signal to the computer to automatically deactivate the computer when the mouse is docked in the docking station.