Abstract: Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked signal of received clock signals by determining a clock signal is running faster than a threshold represented by the clock rate control parameter. The clock rate control controls a circuit clock rate using a selected signal of the clock signals that is not an overclocked signal.

Abstract: A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1?) and second count value (CNT2/CNT2?). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

Abstract: A method and system are provided for thermal management of a CPU. Both hardware and software data are used to periodically calculate a power consumption index. An internal database is provided to convert power consumption data to rotational speed of an associated cooling fan for the CPU. Based upon a change in the calculated power consumption, the rotational speed of the fan may be adjusted to accommodate the change in power consumption. Accordingly, the method and system monitors and adjusts the rotational speed of the cooling fan based upon available hardware and software data.

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Abstract: A computer capable of playing real time applications includes a processing circuit configured to operate in a first power state, a second power state, and a third power state where the processing circuit consumes less power in the second state than in the first state, and less power in the third state than in the second state; and a real time subsystem coupled to the processing circuit, wherein the real time subsystem includes a buffer. The buffer is further configured to store data and output the data to an output device thereby enabling the processing circuit to enter the third power state while the buffer is outputting said data.

Abstract: A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first processor is obtained such that the first processor executes one or more instructions for obtaining the first processor number. Subsequent to obtaining the first processor number, a processor clock value is obtained such that the processor clock value is associated with a processor that executes one or more instructions for obtaining the processor clock value. Subsequent to obtaining the processor clock value, a second processor number associated with a second processor is obtained such that the second processor executes one or more instructions for obtaining the second processor number. If the first processor number and the second processor number are equal, then the first processor number is used to retrieve a compensation value for a normalization operation on the processor clock value.

Abstract: A method of monitoring a computer system for reconfiguration includes defining at least one platform on the computer system, monitoring the platform to gather information related to multiple predefined attributes, analyzing the information related to the multiple predefined attributes based on predetermined threshold values and reconfiguring the platform bases on a result of the analysis. A system for monitoring a computer system for reconfiguration includes a platform defining device adapted to define at least one platform on the computer system, a monitoring device adapted to monitor the platform to gather information related to multiple predetermine attributes an analysis device adapted to analyze the information related to the multiple predetermined attributes based on predetermined threshold values and a reconfiguration device adapted to reconfigure the platform in accordance with a result from the analysis device.

Abstract: One embodiment of the present invention provides a system that facilitates selectively increasing the operating frequency of an electronic circuit, such as a computer system. The system begins by operating in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters the maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state.

Abstract: An image forming apparatus includes a main power supply section, an auxiliary power supply section, a plurality of sensors, and a power control section. The sensors are disposed at a plurality of positions. The sensors change output levels thereof upon detection of a user's operation for initiating an image forming process. The power control section switches the apparatus from a normal operation mode to the power-saving operation mode after a predetermined time period during which no image forming process is performed. The power control section detects the respective output levels of the sensors through sequential power supply from the auxiliary power supply section to the sensors. The power control section switches the apparatus to the normal operation mode upon detection of a change in output level of either one of the sensors.

Abstract: The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch with a clock edge of the clock signal, with the clock edge of the clock signal being shifted in time as a function of a time delay between a signal edge of the input signal at the input and the clock edge, such that the time delay between the signal edge of the data signal and the clock edge is within a predetermined time window.

Abstract: A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test mode, said processor clock control device comprising: a clock signal input operable to receive a slower reference clock signal or a higher speed operational clock signal; at least two clock signal outputs each operable to output a clock signal to a respective domain of said processor; a mode control signal input operable to receive a mode control signal indicating a mode of operation of said processor; a launch control signal input operable to receive a launch control signal, said launch control signal indicating portions of said processor to be tested; and an initiation signal input operable to receive an initiation signal indicating initiation of a processor test; wherein said processor clock control d

Abstract: A method and apparatus for managing power in a server system having clustered server modules. A remote power-on signal delivered to a particular server module is routed to a baseboard management controller (BMC) of the server module. The BMC communicates with a central power management controller (MC) of the server system to ensure that the system currently has sufficient power to power-on the server module.

Abstract: By providing a secure EEPROM (Electrically Erasable Programmable Read Only Memory) device or other non-volatile memory (NVM) as a system operation key (SOK) to control the configurable machine option attributes, various problems associated with machine option configuration and updates may be accommodated. At initial SOK install the identity of the machine is written to the NVM, i.e. the machine serial number. This is performed during the initial machine power up or reboot sequence. As part of the power on or reboot routine the machine will check to ensure no tampering has taken place and that the machine identity and the NVM serial number location data match. A new swapped in SOK can be installed so long as the NVM serial number location has not been previously written to with a conflicting identification number. The machine will then write the serial number to the new SOK thereby protecting it.

Abstract: In accordance with one embodiment of the present invention, a method for recovering a BIOS in a computer is described, comprising: unattendingly loading a BIOS recovery code image into system ROM stored on a bootable device; and unattendingly rebooting the computer.

Abstract: After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU's control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

Abstract: Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.

Abstract: Minimal and maximal numbers are established defining two levels of retry attempts to read system information from a storage medium. Multiple copies of the system information are stored on the storage medium. Attempts are made to successively read the copies until either the system information is successfully read or the system information is not successfully read from any copy of the system information after the minimal number of attempts on each copy. If the system information is not successfully read, attempts are made to successively read the copies until either the system information is successfully read or the system information is not successfully read from any copy of the system information after the maximal number of attempts.

Abstract: A data communications device includes a supervisory circuit, a power supply, and a power circuit. The power circuit includes a data communications port, a power supply connection coupled to the power supply, and a power controller coupled to the data communications port and the power supply connection. The power controller is configured to provide a power signal from the power supply connection to the data communications port in response to communication with the supervisory circuit. Upon loss of communication with the supervisory circuit, the power controller is configured to selectively continue to provide the power signal from the power supply connection to the data communications port when a local parameter has a first value, and discontinue providing the power signal from the power supply connection to the data communications port when the local parameter has a second value.

Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.