Patents Examined by Nitin C. Patel
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Patent number: 7124289Abstract: A framework for automatically provisioning computing devices includes a central database system and a central file system. Information stored in the database comprises a model of the individual devices, as well as the interconnections of the devices. The central file system stores the software components to be installed on the devices. When provisioning is carried out, the database sends commands to agents located on each device which cause them to retrieve and install the software components from the file system, and to configure the components according to the stored model.Type: GrantFiled: October 31, 2000Date of Patent: October 17, 2006Assignee: Opsware Inc.Inventor: Raymond E. Suorsa
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Patent number: 7120814Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.Type: GrantFiled: June 30, 2003Date of Patent: October 10, 2006Assignee: Raytheon CompanyInventors: Frank Nam Go Cheung, Richard Chin
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Patent number: 7120789Abstract: A method and a system for providing a processor to a computer system through a removable CPU module. The processor on the removable CPU module may be shared by multiple computer systems by inserting the module into different computer systems at different times. Upon insertion of the removable CPU module into the computer system, the computer system detects and identifies the module. The computer system may determine a compatibility between the processor and the operating system as well as an access address of the processor, an addressing mode of the processor, a data transfer mode of the processor, etc. The computer system then loads the operating system, informs the operating system of the processors attributes, and initiates execution of the operating system using the processor on the removable CPU module.Type: GrantFiled: August 14, 2003Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Benjamin Andrew Himmel, Maria Azua Himmel, Herman Rodriguez
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Patent number: 7114084Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.Type: GrantFiled: March 6, 2002Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventor: Dumitru Cioaca
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Patent number: 7114090Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.Type: GrantFiled: February 14, 2003Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
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Patent number: 7114086Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated with an instruction buffer is monitored to determine whether power consumption modes can be initiated within a system. If a number of pending instructions within an instruction buffer is greater than a particular threshold value, a normal mode of operation is initiated. If the number of pending instructions is less than the threshold value, the system is put in a reduced mode of operation. In the reduced mode of operation, processing is reduced to lower power consumption within the system. Accordingly, power consumption is altered to match a level of activity within the instruction buffer.Type: GrantFiled: February 27, 2002Date of Patent: September 26, 2006Assignee: ATI Technologies, Inc.Inventors: Carl Mizuyabu, Mark Sternberg, Milivoje Aleksic
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Patent number: 7111181Abstract: The invention is directed to techniques for discovering a powerability condition of a computer network such as the existence of a remotely powerable device attached to a connecting medium of the computer network. Such detection can then control whether a remote power source (e.g., a data communications device such as a switch) provides remote power (e.g., phantom power) to the computer network. One arrangement of the invention is directed to an apparatus for discovering a powerability condition of a computer network. The apparatus includes a signal generator, a detector and a controller which is coupled to the signal generator and the detector. The controller configures the signal generator to provide a test signal to a connecting medium of the computer network, and configures the detector to measure a response signal from the connecting medium of the computer network.Type: GrantFiled: January 14, 2004Date of Patent: September 19, 2006Assignee: Cisco Technology, Inc.Inventor: Robert Bell
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Patent number: 7111178Abstract: A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.Type: GrantFiled: September 28, 2001Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Stefan Rusu, David J. Ayers, James S. Burns
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Patent number: 7107469Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.Type: GrantFiled: July 11, 2003Date of Patent: September 12, 2006Assignee: International Business Machines CorporationInventors: Rafael Blanco, John M. Cohn, Kenneth J. Goodnow, Douglas W. Stout, Sebastian T. Ventrone
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Patent number: 7107479Abstract: A hybrid serial/parallel bus interface method and apparatus for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The method/apparatus is adaptable for either bidirectional or unidirectional applications.Type: GrantFiled: December 2, 2004Date of Patent: September 12, 2006Assignee: InterDigital Technology CorporationInventors: Joseph Gredone, Alfred W. Stufflet, Timothy A. Axness
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Patent number: 7103789Abstract: A method, system, and product are disclosed for indicating a power status of multiple devices using hierarchically encoded indicators. Multiple nodes are included within a data processing system. Each node includes a different implementation of the devices. Each one of a first level of power indicators are associated with a different one of the nodes. Each one of a second level of power indicators is associated with a different one of the devices. A power status of each node is indicated utilizing one of the first level of power indicators. A power status of each device is indicated utilizing the second level of power indicators.Type: GrantFiled: January 13, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: George Henry Ahrens, Jr., Steven Mark Thurber, Ronald Stanley Wesely
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Patent number: 7103791Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.Type: GrantFiled: November 3, 2005Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventor: Feng Lin
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Patent number: 7100066Abstract: Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.Type: GrantFiled: December 27, 2002Date of Patent: August 29, 2006Assignee: LG Electronics Inc.Inventor: Sang Ik Jeong
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Patent number: 7100041Abstract: A computer system 10 with one or more processors 12 can be configured to operate in any one of a number of thermal environments. A setting system 14 sets operating parameters of the computer system such as processor operating voltage and frequency. A selecting system 16 selects values of operating parameters for use in setting by responding to an input of configuring data 20 to select a set of parameter values from a parameter value storage memory 18. The configuring data 20 may be input by the insertion of a smart card 58. Such configuring is useful in adapting computer systems during manufacture for compliance with desired specifications without hardware modification.Type: GrantFiled: April 7, 2003Date of Patent: August 29, 2006Assignee: Sun Microsystems, Inc.Inventor: Paul J. Garnett
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Patent number: 7100037Abstract: A method for reducing BIOS resume time from a computer system sleeping state, and corresponding components and system for implementing the method. The method first identifies an operating system (OS) type running on a computer system. Based on the operating system type that is identified, a set of BIOS resume tasks specific to that operating system type are dispatched for execution in response to a sleep mode wake event. Generally, the OS-type specific BIOS resume tasks may be stored on various storage means, such as BIOS devices, operating system files, or as a carrier wave. In one embodiment, various generic BIOS resume tasks and corresponding dispatch flag data are stored in one or more tables. In another embodiment, various sets of BIOS resume tasks are stored in separate tables or lists, wherein the sets of BIOS resume tasks may be operating system type and/or computer platform type specific.Type: GrantFiled: November 27, 2002Date of Patent: August 29, 2006Assignee: Intel CorporationInventor: Barnes Cooper
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Patent number: 7100067Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.Type: GrantFiled: March 19, 2003Date of Patent: August 29, 2006Inventors: Victor Hansen, Erik Landerholm, Samuel J. Peters, II
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Patent number: 7096375Abstract: A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.Type: GrantFiled: November 19, 2002Date of Patent: August 22, 2006Assignee: Fujitsu LimitedInventors: Shigetoshi Wakayama, Hiroshi Okano, Yoshio Hirose
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Patent number: 7093140Abstract: A computer system includes a voltage regulator that supplies power to a component. The component may provide a signal indicating an amount of current the component consumes under a high utilization operating condition. The voltage regulator may then determine the slope of a load line using this signal.Type: GrantFiled: June 28, 2002Date of Patent: August 15, 2006Assignee: Intel CorporationInventors: Pochang Hsu, Don J. Nguyen
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Method and apparatus for lowering bus clock frequency in a complex integrated data processing system
Patent number: 7093153Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.Type: GrantFiled: October 30, 2002Date of Patent: August 15, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Richard T. Witek, Suzanne Plummer, James Joseph Montanaro, Stephen Charles Kromer, Kathryn Jean Hoover -
Patent number: 7089440Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.Type: GrantFiled: November 24, 2003Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventor: Leon Li-Heng Wu
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Patent number: 4924706Abstract: A method and apparatus for resonant frequency testing of free standing turbine blades made of a material, such as titanium, that is not responsive to a magnetic field is disclosed. A lightweight shim 12 made of a magnetically responsive material such as steel, weighing on the order of 0.5 grams, is attached to the convex side of the blade 10. The shim 12 is excited by an oscillating magnetic field and moves the blade 10 accordingly. The maximum amplitude of blade 10 movement is recorded and used to determine the resonant frequency as the excitation frequency of the magnetic field is swept through a frequency window range. The low weight of the shim 12 does not materially change the resonant frequencies of the blade 10.Type: GrantFiled: April 7, 1989Date of Patent: May 15, 1990Assignee: Westinghouse Electric Corp.Inventor: Donald W. Moore