Abstract: A powered Ethernet connection is provided between two devices connected by an Ethernet connection that provides data communication between the devices. Electrical power is applied to the Ethernet connection at the first device, and extracted from the Ethernet connection at the second device. The extracted power is used to power the second device.

Abstract: An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.

Abstract: A system and method for securing configuration information for a computer system. The method comprises saving configuration information in CMOS memory and automatically programming that configuration information into a non-volatile memory. The system includes a processor, a CMOS memory, and a flash memory. The system also includes a computer-readable medium having computer-executable instructions stored therein for causing configuration information, when saved to the CMOS memory, to be automatically programmed into the flash memory and for causing configuration information stored in the flash memory to be automatically retrieved from the flash memory and written into the CMOS memory every time the computer system is powered on or reset.

Abstract: In accordance with an embodiment of the present invention, a computer system allows an expansion component of the computer system to properly operate even when the computer system is in a low-power mode. According to an embodiment of the present invention, a local system bus has a first section and a second section. An isolation circuit is included which selectively establishes a connection between the first section of the local system bus and the second section of the local system bus during a normal-power mode of the computer system and removes the connection between the first section of the local system bus and the second section of the local system bus during a low-power mode.

Abstract: A computer system includes a memory bus, a memory device and a bridge. The memory device is adapted to furnish a data strobe signal to the memory bus and furnish other signals (to the memory bus) that are indicative of data. The bridge includes a first circuit that is adapted to use the other signals to capture the data in response to the data strobe signal. A second circuit of the bridge is coupled to the first circuit and is adapted to receive a data strobe signal from a memory bus. The data strobe signal is furnished by the memory device and includes a postamble. The second circuit is also adapted to monitor the data strobe signal to detect a signature of the data strobe signal that precedes the beginning of the postamble and prevent the first circuit from responding to the data strobe signal after detection of the signature.

Abstract: An arrangement and a method for synchronizing data to a local clock. The invention incorporates a self-tested self-synchronous two-phase input port, wherein a line or an element of parallel data is tested for data read failure using two different phases or edges of the local clock. If a data read failure is detected using one phase, the other of the two phases is selected for reading the data. The arrangement includes a data read device for reading parallel elements of the data stream using one of two different phases or edges of the local clock, a data read error detecting device arranged to sample at least one element of the data stream using the two different phases or edges of the local clock, and a decision making device.

Abstract: A power supply of a docking system as an extension device of a notebook computer and a power failure safe docking system are disclosed.

Abstract: A computer system includes a processor and a sequential access memory having a boot program stored therein. A boot loader includes a state machine which, in response to initialization of the computer system, controls the sequential access memory to read the boot program and then controls the processor to jump to the boot program in the sequential access memory. The first memory page of the boot program causes further boot code to be transferred to a Random Access Memory (RAM). The processor then jumps to the code in the RAM, which causes the remainder of the boot code to be transferred from the sequential access memory to the RAM and executed.

Abstract: In switching systems, automatic restarts of parts of the system or of the entire system are used for neutralizing software errors. Given an error that is hard to reproduce, the error cannot be neutralized by the above mechanism. This problem is solved by a restart mechanism that only restarts that software of the computer system that allows a continuation of operations of the computer system with reduced functionality.

Abstract: A bootstrap processor selection mechanism for a computer system employs system logic having a memory-mapped sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register. When a reset event is detected, the processors vie for access to the sticky register, using the firmware routine. The first processor that successfully stores its associated processor ID to the sticky register, locks the register against subsequent store operations by the remaining processors. Each processor loads the value stored in the sticky register and compares it with its processor ID to determine whether it is the bootstrap processor.

Abstract: Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit.

Abstract: A communications apparatus having: a communication cable receptacle having signal terminals and power supply terminals for connection to a communication cable having signal lines and power supply lines; a communication interface for transferring a signal to and from an external via the signal terminals of the communication cable receptacle; and one or a plurality of light emitting elements capable of emitting light, the light emitting element being disposed near the communication cable receptacle, being selectively connected to the power supply terminals of the communication cable receptacle, and being capable of displaying at least one of a communication state, a state of the apparatus, an alarm state, and a connection state of the apparatus while receiving a power from the communication cable via the power supply terminals.

Abstract: The present invention relates to a system and method for practically measuring cycle by cycle repeatable system behavior. A set of system parameters is selected for tracking by a group of counters which preferably operate to condense the system state trajectory into a manageable set of counter values thereby forming a counter state. Preferably, repeatability of the counter state practically assures repeatability of the system state trajectory. System repeatability is helpful for debugging purposes since definite identification of a system defect is made easier when a test program failure caused by exercising a defect is repeatable. A test program may be varied for successive runs on a computer system by employing a different randomly or pseudo-randomly generated seed for each run and preferably exercising as many features of the computer system as possible in order to search for defects in the computer system.

Abstract: A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i.e. the read port is unused. For one embodiment of the invention, the selected entry is the zeroth entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.

Abstract: A method or protocol for synchronizing parallel processors in a mobile communication system is disclosed, whereby a sync engine associated with one processor retrieves the current value of a change counter for a database associated with the second processor, stores the current value of the change counter, retrieves all data entries from the database associated with the second processor, and performs a synchronization procedure for a database associated with the first processor based on of all of the data entries retrieved. By examining the change counter, the sync engine can determine whether a user modified a database while the synchronization was in process.

Abstract: A system and method for providing a shortened DSP reset pulse to cause a modem to reset and enter a sleep mode as soon as possible after receipt of an external reset pulse issued by a host. A reset controller detects the external reset pulse, issues a separate reset pulse to the modem, monitors the modem's clock and then terminates the separate reset pulse after a prescribed duration. The prescribed duration is determined by the minimum time required by the DSP to reset. The invention is embodied in a modem connected to an external controller. The modem includes a DSP having a reset terminal and a clock. The DSP begins performing a reset upon a first signal applied to its reset terminal and causes the modem to enter a sleep-mode after a second signal is applied to its reset terminal. The external controller is capable of transmitting an external signal. The reset controller in the modem has a counter and an output node.

Abstract: An interrupt management system includes a first down-counter which decrements in value in response to a clock signal to zero. When the value of the down-counter is equal to zero the down-counter is reset to a predetermined value X and an interrupt request signal is produced. The interrupt management system also includes a second down-counter which decrements in value from a predetermined value Y, where Y>X, in response to the clock signal. The interrupt request signal is received by a processor which services the interrupt and generates an interrupt serviced signal. The interrupt serviced signal is received by a controller which also receive the value of the second down-counter. Using the received value from the second down-counter, the controller can determine if an interrupt request has been missed and also determine the latency period for servicing an interrupt request.

Abstract: In general, a system and method for providing PCI power management support without requiring a clock is disclosed. A computer is allowed to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions. During initiation of the power management system, the system provides a peripheral device with a PME_Status bit. In response to an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer turns back on. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit.

Abstract: A laptop computer system executes automatic battery calibration to improve the accuracy of the battery's internal charge monitor. The calibration procedure drains the battery to approximately 0% of charge capacity during normal computer operation, permitting a user to operate the computer without risking power failure when the battery discharges. The computer returns to normal operation if either the AC power or the battery is removed. During the calibration procedure, the computer system prevents power management software from forcing shut down before the battery completely drains.