Abstract: A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters.

Abstract: A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.

Abstract: A power control unit for a battery-driven data processing system, in which the power consumption of the whole system is prevented from increasing by controlling the clock frequency of a CPU and the brightness of a display unit, is disclosed. When the clock frequency of the CPU is increased, the brightness of the display unit connected to the data processing system having the CPU built therein is decreased while, when the clock frequency of the CPU is reduced, the brightness of the display unit is increased thereby to maintain a substantially constant power consumption. In the case where the brightness of the display unit connected to the data processing system is increased, on the other hand, the clock frequency of the CPU is reduced, while in the case where the brightness of the display unit is reduced, the clock frequency of the CPU is increased thereby to maintain a substantially constant power consumption.

Abstract: Circuitry reduces power consumption by a microprocessor with operand-value-based clock gating. A bit detect unit detects the condition of a pre-determined number of bits of an operand. If the pre-determined number of bits are not necessary for executing the operand, a condition detect signal is generated. Gating logic receives the condition detect signal and initiates a gated clock signal. Latching circuitry or pre-charge circuitry receives the gated clock signal and disables the pre-determined number of bits, preventing the execution of unnecessary bits by the microprocessor and reducing the power consumed during execution. Operation packing improves microprocessor performance by packing narrow-width operations for parallel execution by the microprocessor. A bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates a condition detect signal.

Abstract: Analog and digital power control switching circuits and power strips for use with various electronic devices and electrically operated appliances all enable a first device to control the powering or start-up of other devices. A smart power strip variation enables a user to energize all computer peripherals simply by turning the computer on or off. All embodiments comprise a sensing subcircuit that monitors AC current passed through the device or appliance plugged into a sensing outlet, which, in turn, generates a conditioned DC monitoring signal. A related control subcircuit driven by the monitoring signal powers suitable relays or transistors for activating downstream devices or appliances. All sensing subcircuits comprise a transformer primary, a capacitor, and at least one pair of anti-parallel diodes all connected in parallel. The stepped-up transformer output is rectified and filtered, yielding a DC monitoring signal delivered to the control subcircuit.

Abstract: The present invention provides a system and method for establishing a synchronized time frame for signals in a medical monitoring system. In particular, the present invention provides a system and method for synchronizing the time frame of stimulation signals provided by a stimulator to a subject and response signals received by an amplifier device from the subject in response thereto. Thus, the present invention allows accurate display and analysis of the relationship between stimulation and response signals by a monitoring device. Time frame synchronization of stimulus and response signals is achieved using a periodic bus cycle clock signal which is provided by a bus, i.e., an IEEE 1394 bus, connecting together each of the devices in the monitoring system.

Abstract: Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.

Abstract: For the purpose of providing a method for producing data media, and for providing such data media, by means of which both the need for reinstallation and the time required for restoring a given content to its pre-incompatibility state are minimized, this invention proposes a method for producing such a data medium with a restorable original base data content, whereby, in a section of the data medium designated as the active-data zone, an original base data content is generated, a separate section of the data medium is designated as the recovery zone, and a retrievable backup copy is saved from the active-data zone into the recovery zone.

Abstract: A method and an apparatus for enabling and disabling features in a logical volume management environment is presented. This operation can be performed at boot time or at run time. The user is shown a list of features as well as the current state for each feature. If the feature is currently enabled, the user can select to disable the feature, provided this is a safe operation given the current features for the volume. If the feature is disabled, the user has the following choices: re-enable, disable and retain in the feature stack, disable and remove from the feature stack, and permanently remove the disabled feature from the volume. Disabling or re-enabling features can be very useful to accommodate a changing operating environment. For example, the feature Volume Mirroring allows a replication of the volume at a remote site. If due to network difficulties that remote site becomes inaccessible, then this feature would have to be disabled.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: The invention is directed to techniques for discovering a powerability condition of a computer network such as the existence of a remotely powerable device attached to a connecting medium of the computer network. Such detection can then control whether a remote power source (e.g., a data communications device such as a switch) provides remote power (e.g., phantom power) to the computer network. One arrangement of the invention is directed to an apparatus for discovering a powerability condition of a computer network. The apparatus includes a signal generator, a detector and a controller which is coupled to the signal generator and the detector. The controller configures the signal generator to provide a test signal to a connecting medium of the computer network, and configures the detector to measure a response signal from the connecting medium of the computer network.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: A method for simultaneous start-up of a plurality of processors in a multiprocessing system is disclosed, whereby a special hardware register (e.g., “WhoAmI register”) can be shared by the plurality of different processors. Alternatively, a separate WhoAmI register can be provided for one or more of the different processors. When a processor performs a read operation on a WhoAmI register, the register returns an identification number associated with that processor. Consequently, this processor can perform a set of test and jump instructions to access and execute the appropriate start-up code for this processor. Other embodiments disclosed include a method for distributing interrupts in a multiprocessing system, a method for bus arbitration in a multiprocessing system, and a method for creating atomic instructions that can be used for synchronization in a multiprocessing system.

Abstract: In one embodiment of the invention, a clamping circuit clamps an input signal to reduce overshoot and ringback. A pulse generator generates a pulse signal having a pulse interval from the input signal and a delayed signal. The input signal transitions from a first level to a second level. The delayed signal is derived from the input signal. A controller generates a control signal responsive to the pulse signal. A switching circuit clamps one of the overshoot and the ringback of the input signal within the pulse interval upon receipt of the control signal.

Abstract: A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.

Abstract: The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher than its rated or assigned speed. An important feature of the present invention is that it is internal to the computer system on which it operates. That is, the test of the present invention is implemented in the computer system's Basic Input/Output System or as microcode stored directly on the CPU. The end user need not resort to any external means such as a floppy or CD disk to test the CPU included in his/her computer system. If the CPU is not overclocked, the test runs invisible to the end user. If, on the other hand, the CPU is overclocked, the test allows the user to either continue with the normal boot up process or exit the boot up process to adjust the running speed to substantially match the assigned speed of the CPU.

Abstract: User provided product configurations are identified and memorized along with their corresponding configuration information such as constraints and incompatibilities. The next time that configuration is provided by a user, the corresponding configuration information can be retrieved from memory so that a configuration engine will not need to be accessed. Retrieving the corresponding configuration information from memory as opposed to recomputing them with a configuration tool requires less time and avoids tying-up scarce configuration resources. Factors such as frequency and recentness can be considered in determining which configurations to memorize. Each time a particular configuration is provided, a counter associated with that configuration is incremented. Thus, within any given period of time, the number of times that particular configuration has been selected can be determined. Long-term frequency counts can track the most selected product configuration over a longer period of time.

Abstract: In one embodiment, an integrated circuit device comprises a trusted platform module and a boot block memory unit covered by a common package. The boot block memory unit is in communication with the trusted platform module and provides boot information to the trusted platform module. An example of the boot information includes a boot block code.

Abstract: A method and an apparatus for providing a float voltage potential in a bus connection are described. In one embodiment, a device has a first input, a second input, and an output. The first input is coupled to a first power supply and the second input is coupled to a second power supply. The device is configured to provide a float voltage potential at the output when the first and second power supplies supply the power at different time.

Abstract: A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.