Abstract: A method and system that synchronizes time-related data in a digital processing system. The data to be synchronized includes display data such as audio or video data and command data such as uniform resource locators. The data is encoded with time indicators that allow the media data, through the execution of a set of instructions, to be processed synchronously with the display data.

Abstract: Computer systems and methods of data processing are disclosed in which fault/event management is carried out in accordance with a configurable fault recovery policy. In addition, computer systems and methods of data processing are disclosed in which hierarchical levels of fault management (or more generally “event” management) are provided in accordance with the configurable fault policy.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Abstract: A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.

Abstract: An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.

Abstract: A portable electronic device is disclosed that is reprogrammable through a pager network. The device includes a communications port. The device also includes a data transceiver for transmitting send data and receiving receive data from a pager network. In addition, the device has a processor. The processor is in electronic communication with the communications port for communicating through the communications port. The processor is also in electronic communication with the data transceiver for communications with the pager network. The device also includes reprogrammable memory programmed with instructions to cause the device to receive new program code from the pager network and to reprogram the reprogrammable memory with the new program code.

Abstract: A data communications device includes a supervisory circuit, a power supply, and a power circuit. The power circuit includes a data communications port, a power supply connection coupled to the power supply, and a power controller coupled to the data communications port and the power supply connection. The power controller is configured to provide a power signal from the power supply connection to the data communications port in response to communication with the supervisory circuit. Upon loss of communication with the supervisory circuit, the power controller is configured to selectively continue to provide the power signal from the power supply connection to the data communications port when a local parameter has a first value, and discontinue providing the power signal from the power supply connection to the data communications port when the local parameter has a second value.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: A data processing system and method are disclosed for generating and displaying a local server clock which is synchronized with a server clock using a client clock. The data processing system includes a server computer system, which includes a server clock, and a client computer system, which includes a display and a client clock. Data is requested by the client from the server computer system to be displayed on the client computer system's display. The data is then received in the client computer system. The client computer system determines a current time indicated by the server clock. The client computer system generates a local server clock. Thereafter, the local server clock is updated utilizing the client clock. The local server clock and the data are then displayed together on the client's display.

Abstract: The present invention provides a method for reducing the amount of power consumed by an optical disk player. The method provides: recording at least a portion of the audio, video, or audio/video data from an optical disk onto the portable computer's hard disk while the optical disk is being played over the output device; turning the drive's spin motor off as soon as the data has been transferred to the hard disk; and then continuing to play the remaining un-played portion of the optical disk over the portable computer's speaker or other output device from the hard disk. The method further comprises recording in an index database a title of the optical disk and a title of the track written to the hard disk, and playing the data from the hard disk without re-reading the optical disk if the data has been previously written to the hard disk.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A method for enabling communication between system BIOS and a graphics device is described herein. In one embodiment, a graphic device sets a system management interrupt (SMI) bit in an interface register located at a predetermined address of a configuration space of a predetermined peripheral device, which triggers an SMI interrupt. As a result, a system BIOS SMI handler is invoked to perform certain operations, including configuring a local memory of the graphics device.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: A method and apparatus for distributing power to a plurality of computers in a network. A power management system including a feed-back mechanism, is employed to monitor power consumptions of the plurality of computers. Should the overall power consumption reach a threshold, the power management system instructs the microprocessors in the plurality of computers to enter into a lower power state, such as a sleep state, for a certain duration, thus lowering overall power.

Abstract: Disclosed is a method for automatically re-provisioning an appliance server without significant user-interaction. The disk drive of a server to be utilized as an appliance server is partitioned into at least three partitions, including a systems partition, a network operating system partition, and an images partition. A re-provisioning utility is provided, which, when activated by a user, removes the present application from the server and forwards it to a storage location on the network or in a fourth storage partition and installs another application on the server. The system is re-booted and re-configured to provide full operation of the new application.