Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A data carrier that communicates confidential data is configured to mask process-dependent power consumption by using power stored in an internal capacitor. The capacitor is initially charged to the voltage of an external power source, and then decoupled from the external power source. The capacitor provides power to an internal processor, and consequently discharges gradually. At the end of a given time interval, the capacitor is discharged to a fixed voltage, then charged to the supply voltage. In this manner the power consumed by charging of the capacitor is decoupled from the power consumed by the processor. If the capacitor drops below a threshold voltage before processing is completed, the processor is halted. To optimize the available processing time, the time interval before discharging the capacitor to the fixed voltage is dynamically adjusted to reduce the time that the processor is halted.

Abstract: Embodiments of the present invention describe a system and method for microprocessor power regulation. An appropriate amount of voltage is provided to a microprocessor based on a voltage identifier (VID) received by a voltage controller from the microprocessor via a serial communication line. A voltage identifier clock signal (VIDClock) is used for the timing of transmission and receipt of data/acknowledgement signals. A guard clock signal (VIDGuard) is provided via a separate guard clock line to prevent potential noise on the clock line from causing a clock signal misidentification, which could cause a wrong value to be received as the VID. VIDGuard is analyzed in relation to ViDClock to verify the value of the clock signal. To verify receipt of the VID data, a voltage identifier acknowledgement line (VIDAck) is transmitted from the voltage regulator to the microprocessor. The acknowledgement signal is checked by a two-part receipt verification, high-to-low and low-to-high.

Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory modules is provided. Because different memory modules may have different CAS latencies, multilevel signaling is used to standardize the CAS latencies throughout the system. A static pin is provided on each memory device such that a drive signal can be received. The voltage level of the drive signal corresponds to a selected CAS latency for the system.

Abstract: An output device (103,104) can be quickly and easily set to the operating parameters required for a particular output process. The output device has RAM (204) that temporarily stores the control parameters, and flash ROM (206) that stores the same parameter values in a nonvolatile manner. Specific parameter values are stored in RAM (204) in response to a specific command from the host (102). A customization command causes the output device (103,104) to save the operating parameters from RAM (204) into the flash ROM (206). Another customization command causes the output device (103,104) to restore the parameters from flash ROM (206) to RAM (204). A particular operating environment defined by the parameters stored in nonvolatile memory can therefore be quickly reset en masse.

Abstract: The invention is directed to techniques for discovering a powerability condition of a computer network such as the existence of a remotely powerable device attached to a connecting medium of the computer network. Such detection can then control whether a remote power source (e.g., a data communications device such as a switch) provides remote power (e.g., phantom power) to the computer network. One arrangement of the invention is directed to an apparatus for discovering a powerability condition of a computer network. The apparatus includes a signal generator, a detector and a controller which is coupled to the signal generator and the detector. The controller configures the signal generator to provide a test signal to a connecting medium of the computer network, and configures the detector to measure a response signal from the connecting medium of the computer network.

Abstract: Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

Abstract: A method and system for recovering a master boot record within a data processing system. In accordance with the method of the present invention, a master boot record recovery setup utility is invoked by a user. In response to invoking the master boot record recovery utility, the master boot record in a first bootable device is copied to an alternate non-volatile storage device. A recovery flag is set within BIOS indicating that the MBR has been securely copied. In response to a failed boot attempted from the first boot device, the copy of said master boot record within said alternate non-volatile storage device is accessed and utilized to boot the system.

Abstract: Disclosed is a signal processing apparatus in which it is possible to obtain a favorable system construction in a case where the main unit of the apparatus and an external device have been connected via a digital interface in the recording standby mode. The signal processing apparatus is capable of constructing a network by being connected to a plurality of external devices. In a case where at least connection to an external device has been sensed when the apparatus is in an operation standby state, power shutdown is restricted to thereby curtail bus reset of the network.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: An object of the present invention is to enable precise and easy adjustment of clock skew. A clock distribution circuit is designed and the placement and routing of the entire chip including the clock distribution circuit follows. Then the clock skew value is calculated and whether the calculated clock skew exceeds a target value is checked. When the clock skew exceeds the target value, the outputs of some driver elements are disconnected or connected to adjust the clock skew. The steps disconnecting or connecting the outputs of the drivers are repeated until the clock skew becomes equal to or smaller than the target value.

Abstract: An agent is downloaded from a server to a client before installation. Then, the agent executes installation of an install file into the client by referring to a managing record file and according to an execution script. The agent updates the managing record file according to an install execution state of the client. When downloaded again from the server to the client after reboot, the agent continues the installation of the install file by referring to the managing record file and according to the execution script, and further updates the managing record file according to an install execution state of the client.

Abstract: A programmable interface controller for transmitting data to an output device that is suitable in both fully synchronous systems and in systems that span clock domains. The illustrative embodiments comprise: receiving a plurality of field identifiers and an indication of an order by which each of the plurality of field identifiers is to be uniquely associated with each field in a sequence of fields; receiving a stream of data that comprises the sequence of fields and an indication of the boundary between successive fields in the sequence of fields; and processing each field in the stream of data in accordance with the field identifier uniquely associated with that field.

Abstract: A method that includes receiving a function call from an administrator at a computer system is provided. The function call includes an argument. A function identified by the function call is executed in response to receiving the function call. Information is transferred from a location identified by the argument to the computer system in response to the function being executed.

Abstract: A method for altering the start-up sequence of an operating system prior to loading the operating system is disclosed. The method allows changes to be made to the start-up sequence of processes and applications initiated by the operating system based upon the occurrence of a designated event during the BIOS boot sequence. In this manner, events occurring prior to operating system loading affect the operating system start-up sequence. Similarly, the illustrative embodiment of the present invention may, during the period of time the operating system is operating, write instructions which control the sequence of events taking place during the subsequent BIOS boot sequence.

Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency.

Abstract: An apparatus and method for compensating skew across a plurality of data interfaces includes using a recovered clock signal at an incoming clock rate to regulate output from a deskew interface. The recovered clock is drawn from one of the data interfaces and the data from all the data interfaces is deskewed to the recovered clock signal. A deskew buffer is provided for each data interface. Link logic may also be run in accordance with the recovered clock signal. Alternatively, the link logic may run at a local clock rate and an elastic buffer is coupled between the deskew interface and the link logic.

Abstract: The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.