Abstract: The disclosure describes a heat-dissipating object having a reservoir structure so that a reservoir system can be formed in an electronic device, allowing for a liquid TIM in the gap between the heat-dissipating object and the electronic device. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a tube for taking in a liquid material and releasing it again when needed. A heat-dissipating object, including a heat sink, a cold plate and a vapor chamber and an electronic device, including a flip chip package and a lidded flip chip package are particularly described in details of the embodiments of the present invention.

Abstract: A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.

Abstract: A semiconductor package includes: a connection structure including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip having connection pads connected to the redistribution layer; an encapsulant encapsulating the semiconductor chip; first and second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in regions of the first and second pads; first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Abstract: A method of processing a double sided wafer of a microelectromechanical device includes spinning a resist onto a first side of a first wafer. The method further includes forming pathways within the resist to expose portions of the first side of the first wafer. The method also includes etching one or more depressions in the first side of the first wafer through the pathways, where each of the depressions have a planar surface and edges. Furthermore, the method includes depositing one or more adhesion metals over the resist such that the one or more adhesion metals are deposited within the depressions, and then removing the resist from the first wafer. The method finally includes depositing indium onto the adhesion metals deposited within the depressions and bonding a second wafer to the first wafer by compressing the indium between the second wafer and the first wafer.

Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.

Abstract: An interconnection structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing toward the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a recess. A portion of the first dielectric layer is disposed within the recess.

Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

Abstract: A contact structure of a semiconductor device includes a gate contact in contact with a gate structure and extending through a first dielectric layer, a source/drain contact in contact with a source/drain feature and extending through the first dielectric layer, a common rail line in contact with the gate contact and the source/drain contact, and a power rail line in contact with the common rail line and electrically coupled to a ground of the semiconductor device.

Abstract: A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant.

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A power electronics assembly is provided with a self-healing feature. The power electronics assembly may include a semiconductor electronics device and an insulating substrate coupled to the semiconductor electronics device. A base metal structural component may be provided, coupled to the insulating substrate. The assembly may include a frame component cooperating with the base metal structural component and defining an enclosure containing the semiconductor electronics device and the insulating substrate. The assembly further includes a self-healing polymer comprising disulfide bonds. The self-healing polymer is disposed within the enclosure; additional potting material may also be provided as a multi-layered encapsulation. In various aspects, the self-healing polymer may include polydimethylsiloxane based polyurethane (PDMS-PU) modified with disulfide bonds. The frame component may be configured to direct or confine heat to areas of the assembly where ESD may be problematic.

Abstract: The disclosure provides a heat conduction structure with higher heat conductivity. This embodiment is a heat conduction structure where heat is conducted from a first member to a second member. The heat conduction structure includes at least one self-assembled monolayer and a heat dissipation grease. The self-assembled monolayer is formed on at least one surface of the first member and the second member. The heat dissipation grease is disposed between the first member and the second member. The heat dissipation grease is in contact with the self-assembled monolayer.