Abstract: A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps. A plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator. A variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished. The plasma is then powered with substantially magnetic energy.

Abstract: The present invention is generally directed to a novel gas delivery system for various deposition processes, and various methods of using same. In one illustrative embodiment, a deposition tool comprises a process chamber, a wafer stage adapted for holding a wafer positioned therein, and a gas delivery system positioned in the chamber above a position where a plasma will be generated in the chamber, wherein substantially all of a reactant gas is delivered into the chamber via the gas delivery system. In another illustrative embodiment, the reactant gas exiting the gas delivery system is directed so as to cover substantially all of an area defined by an upper surface of the wafer.

Abstract: A method for fabricating a flash memory device by determining the active region width (10) of a semiconductor device (27) using a measuring technique for the source drain overdrive current elements (31, 32, 33) having different active region widths and using that difference to establish the difference between the active region width of the devices (31, 32, 33) and the drawn width and using the difference to establish the actual width (10) from drawn width in future devices, and a device thereby fabricated.

Abstract: A method for providing a precursor to a supercritical processing chamber is provided. The precursor in solid form is provided in an ampoule external to the supercritical processing chamber. A fluid is provided to the ampoule, where at least a portion of the gas enters the solid precursor causing a melting point of the precursor to be depressed and thereby causing the solid precursor to melt. The melted precursor is delivered to the supercritical process chamber.

Abstract: Precursor compositions for the CVD formation of low k dielectric films on a substrate, e.g., as an interlayer dielectric for fabrication of microelectronic device structures. The precursor composition includes a gaseous mixture of (i) at least one aromatic compound, (ii) an inert carrier medium and (iii) optionally at least one unsaturated constituent that is ethylenically and/or acetylenically unsaturated The unsaturated constituent can include either (a) a compound containing ethylenic unsaturation and/or acetylenic unsaturation, or (b) an ethylenically unsaturated and/or acetylenically unsaturated moiety of the aromatic compound (i) of the precursor composition. The low k dielectric film material may be usefully employed in integrated circuitry utilizing copper metallization, to achieve low RC time constants and superior microelectronic device performance.

Abstract: A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operat

Abstract: Oxide particles with a doping component distributed in the core and a shell surrounding the core, which can be prepared by first introducing the doping into the core of a metal oxide or metalloid oxide via an aerosol in a pyrogenic process, subsequently coating the doped core with a salt solution of a metal or metalloid, drying it and optionally calcining it; which particles can be employed for chemical-mechanical polishing.

Abstract: A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer (7) on the silicon-germanium layer (6) and patterning the resultant structure (8), whereafter the dielectric layer (7) and the silicon-germanium layer (6) are etched away within a predetermined region (9). Preferably, the silicon-germanium layer (6) is amorphous, whereby the dielectric layer (7) is deposited on the amorphous silicon-germanium layer (6) in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

Abstract: A semiconductor-manufacturing tool has two load locks, one for semiconductor wafers entering the tool for processing and the other for wafers leaving the tool after being processed. The load locks are of a new generation capable of being evacuated or vented in shorter times than load locks of the prior art, and permit high throughput. The tool is associated with three atmospheric wafer-handling robots to obtain the high throughput permitted by the load locks. One robot transfers wafers to be processed from a supply to a wafer pre-aligner, another robot transfers wafers from the wafer pre-aligner to the load lock for wafers entering the tool, and the third transfers processed wafers from the load lock for wafers leaving the tool back to the supply.

Abstract: A method and apparatus for identifying individual semiconductor die that originate from a semiconductor substrate containing a plurality of die is disclosed. Aspects of the invention include physically associating a respective die ID with at least a portion of individual die on the wafer, and storing the die ID and wafer fabrication information in a database. During subsequent testing of the die, the die ID is used to retrieve the wafer fabrication information from the database, thereby aiding a determination as to a cause of a failure of the die.

Abstract: A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps.

Abstract: The invention includes reactive gaseous deposition precursor feed apparatus and chemical vapor deposition methods. In one implementation, a reactive gaseous deposition precursor feed apparatus includes a gas passageway having an inlet and an outlet. A variable volume accumulator reservoir is joined in fluid communication with the gas passageway. In one implementation, a chemical vapor deposition method includes positioning a semiconductor substrate within a deposition chamber. A first deposition precursor is fed to an inlet of a variable volume accumulator reservoir. With the first deposition precursor therein, volume of the variable volume accumulator reservoir is decreased effective to expel first deposition precursor therefrom into the chamber under conditions effective to deposit a layer on the substrate.

Abstract: The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece including: a substrate having a surface; a temperature sensing device borne by the substrate; and an electrical interconnect formed upon the surface of the substrate, the electrical interconnect being electrically coupled with the temperature sensing device. In another aspect, a method of sensing temperature of an electronic device workpiece includes: providing an electronic device workpiece; supporting a temperature sensing device using the electronic device workpiece; providing an electrical interconnect upon a surface of the electronic device workpiece; electrically coupling the electrical interconnect with the temperature sensing device; and sensing temperature of the electronic device workpiece using the temperature sensing device.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A wafer processing apparatus comprising a wafer stage, wherein a semiconductor wafer is mounted on the wafer stage so as to process the semiconductor wafer, wherein a holding mechanism of the wafer stage is commonly used for a plurality of wafer stages, and accordingly, the wafer stage can be changed into a wafer stage having a different function so as to process the semiconductor wafer.

Abstract: A method for controlling the variation in process parameters using test structures sensitized to process parameter changes. Wavefront engineering techniques are used to make features of the test structure more sensitive to process changes. Focus and exposure parameters are adjusted in response to the measurements of the test structures. In another embodiment, the wavefront engineering features are placed to permit the test structure appearing on the reticle out of focus. The wavefront engineering feature is an OPC technique applied to the test structure to modify it. The OPC features are applied in an asymmetrical manner to the test structure and enable identifying the direction of process focus changes.

Abstract: A pixel unit included in a multi-domain vertically aligned liquid crystal display is provided. The pixel unit includes a first insulating substrate having a first side and a second side, a second insulating substrate having a third side and a fourth side, a plurality of liquid crystal molecules filled between the first side of the first insulating substrate and the fourth side of the second insulating substrate, an electric field generation device for providing an electric field to change alignment of the liquid crystal molecules, and a cone protrusion formed on the first side of the first insulating substrate for generating an advance inclination of the liquid crystal molecules around the cone protrusion.

Abstract: A method of manufacturing a compound layer, containing a nitrified metal as a mayor component thereof and having a predetermined microstructure pattern, includes: an ion implantation step for implanting hydrogen ions into a predetermined region of a compound layer formed on a substrate to form an implanted region; and an etching step for selectively etching the implanted region by using a gas containing at least oxygen, to remove the implanted region of the compound layer while maintaining the other region as a microstructure pattern. By introducing a halogen element like fluorine in addition to hydrogen, fabrication of the pattern can be executed more reliably and more easily. As a result, volatility of reaction products produced upon etching the compound layer is enhanced, and micro-loading effects are suppressed.

Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.

Abstract: A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same is disclosed. The wafer-on-wafer package can be burned-in and tested at the wafer level prior to segmenting, or singulating, the wafer-on-wafer package into a plurality of individual chip-scale packages.