Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A method of forming a low dielectric constant silicate material for use in integrated circuit fabrication processes is disclosed. The low dielectric constant silicate material is formed by reacting by reacting a gas mixture comprising an organosilane compound, an oxygen source, and an inert gas. Thereafter, a silicon carbide cap layer is formed on the silicate material by reacting a gas mixture comprising a silicon source and a carbon source. The silicon carbide cap layer protects the underlying organosilicate layer from cracking and peeling when it is hardened during a subsequent annealing step.

Abstract: A method for monitoring silicide failures in the semiconductor process provides P-channel gate oxide capacitors on a semiconductor wafer. The breakdown voltages of the P-channel oxide gate capacitors are measured. With higher rapid thermal anneal (RTA) temperatures, an increased number of short failures occur in the P-channel gate oxide capacitors. Based on a correlation of the P-channel gate oxide capacitor failures and the RTA temperatures, the optimum RTA temperature for the silicide process is determined.

Abstract: A system for regulating temperature of a developer is provided.

Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.

Abstract: In cleaning a substrate which has a metal material and a semiconductor material both exposed at the surface and which has been subjected to a chemical mechanical polishing treatment, the substrate is first cleaned with a first cleaning solution containing ammonia water, etc. and then with a second cleaning solution containing (a) a first complexing agent capable of easily forming a complex with the oxide of said metal material, etc. and (b) an anionic or cationic surfactant.

Abstract: Disclosed is a method for characterizing the quality of microelectronic features using broadband white light. A highly collimated light source illuminates an area of a first wafer using broadband multi-spectral light. The angular distribution of the light scattered from the first wafer is then measured. Generally, the angle of the light source, detector, or both is altered and an angular distribution measurement taken at each angle, producing a scatter signature for the first wafer. Finally, the scatter signature of the first wafer is compared with a known scatter signature of a second wafer of good quality to determine the quality of the first wafer.

Abstract: An anti-reflection film of an organic compound is formed on a substrate. The anti-reflection film is weakened by carrying out plasma processing on the anti-reflection film, and then, a resist film is formed on the weakened anti-reflection film. The resist film is subjected to pattern exposure and development so as to form a resist pattern from the resist film. The anti-reflection film is dry etched by using the resist pattern as a mask, so as to pattern the anti-reflection film.

Abstract: A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer.

Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions.

Abstract: A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator.

Abstract: A single-substrate-heat-processing method performs a reformation process for a tantalum oxide film on a wafer and a crystallization process for this film in this order. In the reformation process and crystallization process, a heater is set at preset temperatures substantially equal to each other, and a pressure in a process chamber is set at first and second process pressures different from each other. A density of a gas present between a support surface and the wafer is changed by using the pressure in the process chamber as a parameter, and thus a heat transfer rate between the support surface and wafer is changed, thereby setting a wafer temperature at first and second process temperatures different from each other.

Abstract: The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece including: a substrate having a surface; a temperature sensing device borne by the substrate; and an electrical interconnect formed upon the surface of the substrate, the electrical interconnect being electrically coupled with the temperature sensing device. In another aspect, a method of sensing temperature of an electronic device workpiece includes: providing an electronic device workpiece; supporting a temperature sensing device using the electronic device workpiece; providing an electrical interconnect upon a surface of the electronic device workpiece; electrically coupling the electrical interconnect with the temperature sensing device; and sensing temperature of the electronic device workpiece using the temperature sensing device.

Abstract: The present invention is directed to a method of using scatterometry measurements to control deposition processes, and a system for accomplishing same. In one embodiment the method comprises forming at least one grating structure above a substrate, performing a deposition process to form a process layer above the grating structure, and illuminating the process layer and the grating structure. The method further comprises measuring light reflected off of the process layer and the grating structure after the deposition process is started to generate an optical characteristic trace for the process layer and the grating structure comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a process layer having a desired profile, and stopping the deposition process based upon the comparison of the generated trace and the target trace.

Abstract: A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same. The wafer-on-wafer package can be burned-in and tested at the wafer level prior to segmenting, or singulating, the wafer-on-wafer package into a plurality of individual chip-scale packages. The device wafer includes a plurality of unsingulated semiconductor dies having a plurality of die bond pads being respectively bonded to a plurality of electrically conductive die bond pad connect elements provided on a first surface of the support wafer. The die bond pad connect elements are in electrical communication with a plurality of respectively associated test connection/mounting elements positioned in a prearranged pattern on the opposite surface of the support wafer.

Abstract: A method is provided for manufacturing, the method including processing a workpiece in a plurality of processing steps and measuring characteristics of the processing performed on the workpiece in at least two of the plurality of processing steps. The method also includes displaying the characteristics measured by overlaying the characteristics measured at each of the at least two of the plurality of processing steps to display a final resulting workpiece.

Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Abstract: Semiconductor chips 15 are separated from one another by cutting a semiconductor wafer along scribing lines, and are fitted in recesses 11 formed in a contactor 10. Bump electrodes 13 are brought into contact with the pad electrodes of the semiconductor chips, so that the former electrodes are electrically connected to the latter electrodes. Each of the recesses of the contactors are surround by side walls which are trapezoid in section. Hence, the side walls can be readily fitted in the grooves formed along the scribing lines; that is, the semiconductors 15 can be fitted in the recesses 11 with ease. The contactor 10 and the dicing sheet having the semiconductor chips 15 are pressed against each other, so that the electrode connection is positively achieved.

Abstract: A method of supporting a semiconductor substrate according to the present invention can be applied to the step of processing the semiconductor substrate at a high temperature of 350° C. or higher, and there is provided a process for the production of electronic parts, comprising the steps of forming semiconductor circuits on one surface (surface A) of a semiconductor substrate (SEC) having a thickness of at least 0.2 mm, supporting the semiconductor substrate on a supporting substrate (BP) by bonding (AS) of said surface A to the supporting substrate (BP), grinding and polishing the exposed other surface (surface B) of the semiconductor substrate (SEC) by a physical method, a chemical method or a method of combination of these methods, to decrease the thickness of the semiconductor substrate (SEC) to less than 0.

Abstract: An ion implanter vacuum integrity check process and apparatus that enables a vacuum integrity check at a pressure substantially below the ion implantation process pressure, while storing an ion implantation process pressure set point for a subsequent ion implantation process. An ion implanter includes an end station chamber, a high vacuum system, a disk, a gas supply system and a controller for storing at least a vacuum integrity check pressure set point and an ion implantation process pressure set point. A disk inserted into the end station is accelerated to a predetermined rotational speed, while the high vacuum system is used to pump down the end station chamber. The end station chamber is, then, purged with an inert gas for a first predetermined time period, while maintaining the disk rotational speed and continuing to pump down the end station chamber. The pressure of the end station chamber is monitored, while the disk rotational speed and pumping of the chamber are maintained.