Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.

Abstract: In a water rinsing process performed after the surface of a substrate has been cleaned using a cleaning solution, a first spinning process, in which water is supplied to the surface of the substrate while the substrate is rotated at a first rotation speed, and a second spinning process, in which the substrate is rotated at a second rotation speed that is higher than the first rotation speed, are repeatedly performed alternately.

Abstract: A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.

Abstract: A method and an apparatus for performing trench depth analysis in semiconductor device manufacturing. A first processing on at least one semiconductor wafer is performed. Optical trench data is acquired from the processed semiconductor wafer. An optical trench analysis, based upon the optical trench data, is performed. A corrective feedback step is performed during a second processing of the semiconductor wafer in response to the optical trench analysis.

Abstract: A method of nitriding a silicon oxide film according to the present invention includes flowing a nitrogen-containing gas into a substrate processing chamber and forming a plasma from the gas. Optical emissions from the plasma are then measured while a silicon oxide film deposited over a substrate disposed in the chamber is exposed to the plasma to obtain OES data that is used to optimize, monitor and/or stop the nitriding process.

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.

Abstract: The present invention is generally directed to various methods for calibrating optical-based metrology tools. In one illustrative embodiment, the method comprises performing a metrology process on a specimen using an optical-based metrology tool to obtain optical characteristic data and comparing the obtained optical characteristic data to target optical characteristic data established for the specimen.

Abstract: Inspection of a semiconductor wafer is performed while a manufacturing process of another semiconductor wafer is executed. A plurality of semiconductor wafers are mounted on a semiconductor manufacturing apparatus and, while semiconductor the manufacturing process is executed, an arbitrary semiconductor wafer is removed from among the semiconductor wafers having finished the manufacturing process, to a position that is different from a position on the manufacturing apparatus defined for the plurality of semiconductor wafers. Inspection is then done for the removed wafer and, if it is evaluated as good, it is first returned to the position from which the wafer has been removed and then returned, along with the other semiconductor wafers to the original position on the manufacturing apparatus.

Abstract: An in-process test sequence for integrated circuit chips that can be used to provide more accurate test results when the integrated circuit device properties are temporarily altered during the fabrication process. The test sequence comprises special Kerf tests for device property and metallurgy, slow speed tests to determine device and chip connectivity, and a final high performance test after the module is assembled. Device properties are tested via special Kerf sites before formation of a temporary material that may increase the capacitive load of the circuits and adversely impact the device properties. The in-process slow speed tests are designed to test the chips and devices at a speed substantially slower than their rated speeds so as to reduce the impact of the increase in capacitive load brought about by the temporary support material. After the module is assembled and temporary material removed, the module is exercised at its rated speed in a high final performance test.

Abstract: A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.

Abstract: A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features (50, 52, 70) in a region of a semiconductor substrate (40, 60) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate (40, 60) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features (50, 52, 70) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features (50, 52, 70) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features.

Abstract: A method and an apparatus for correlating error data with detect data. A semiconductor wafer in a first lot is processed. Defect data based upon analysis of the processed semiconductor wafer is acquired. Electrical test data based upon analysis of the processed semiconductor wafer is acquired. The electrical test data is acquired by performing a wafer electrical testing process on the processed semiconductor wafer. The electrical test data is correlated with the defect data to produce correlated data. At least one of the following is performed: a yield prediction or the performance prediction of a second lot based upon the correlated data. The yield prediction comprises predicting a percentage yield of acceptable semiconductor wafers in the second lot. The performance prediction comprises predicting the performance of the acceptable semiconductor wafers.

Abstract: 12 Methods of forming features in polymeric materials by laser ablation techniques alone, or by the combined use of laser ablation techniques and photolithography, are disclosed. The methods can be used to pattern non-photosensitized materials, as well as photosensitized materials. The patterned features can have different shapes, dimensions and aspect ratios in the same polymer layer. Structures including the patterned features can include multiple layers formed of photosensitized and/or non-photosensitized polymer materials.

Abstract: A method of process control includes the steps of preparing recycling procedure data for each type of film formed on a wafer by diffusion processing, setting a recycle control number for controlling recycling processing based on the recycling procedure data, and outputting a recycling instruction to the recycling apparatus when the prescribed number of non-product wafers are accumulated and when an accept request is received from the recycling apparatus.

Abstract: A substrate defining an insulating surface layer portion and formed with a wiring groove filled with a wiring line the wiring line is electrically connected to a conductive member. The conductive member occupies an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface. An insulating first film is formed on the first surface. A via hole is formed through the first film. The via hole is formed so that a boundary between the wiring line and the insulating surface layer portion passes through the inside of the via hole. The bottom of the via hole is observed with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons, to judge whether a state of the bottom of the via hole is accepted or rejected.

Abstract: A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process segments. Each respective process segment is performed for a respective processing interval. The method includes the steps of: (a) determining a relationship among respective process intervals for at least two particular process segments of the plurality of process segments; (b) determining a first respective process interval required for a first particular process segment to effect a desired result in the semiconductor component; and (c) using the relationship to establish the respective process interval required for at least one selected particular process segment in order to fix the respective process interval for a controlled process segment other than the at least one selected particular process segment.

Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

Abstract: The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.