Abstract: First of all, a semiconductor substrate having a metal contact thereon is provided. Then a protecting layer is formed on the semiconductor substrate and the metal contact. Afterward, an etching process is performed to etch through the protecting layer until exposing a partial surface of the metal contact, so as to form and define a predetermined opening in the protecting layer, wherein an etching-reactive layer is formed on the protecting layer after finishing the plasma etching process. Finally, a stripping process is performed to remove the etching-reactive layer on the protecting layer and form a contact window and a metal contact thereof without fluoride, whereby it is avoided reacting the etching remainder with the metal pad during the follow-up process.

Abstract: An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.

Abstract: A plasma ashing process and apparatus for selectively ashing photoresist and/or post etch residues from a semiconductor substrate includes generating a reduced ion density plasma in a plasma generation region at a pressure of at least 2 torr greater than the processing chamber pressure; and exposing the wafer surface having the photoresist and/or post etch residues thereon to the reduced ion density plasma to selectively remove the photoresist and/or post etch residues from the surface and leave the surface substantially the same as before exposing the substrate to the reduced ion density plasma.

Abstract: A method for forming a vertical edge submicron through-hole comprises the steps of; forming a hole on a sample thin film with a larger diameter than design size of a through-hole, with a bottom having a thickness close to the design size remaining, by etching using a focused ion beam device; forming a through-hole with the design size on the bottom section by focused ion beam etching; and backfilling the large hole to the design size by deposition using a focused ion beam device.

Abstract: Provided herein is a wafer carrier comprising a disk and a pocket, wherein the pocket is centered in the disk and holds a wafer. Also provided is a method of processing or testing a wafer for a semiconductor device, comprising the steps of placing the wafer in the wafer carrier disclosed herein; loading the wafer carrier in a loadlock chamber; and transferring the wafer carrier from the loadlock chamber to a process chamber for processing or testing.

Abstract: A method for characterizing an interconnect structure profile includes providing a wafer having a grating structure including a plurality of interconnect structures; illuminating at least a portion of the grating structure; measuring light reflected from the grating structure to generate a reflection profile; and determining a profile of the interconnect structures based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure including a plurality of interconnect structures includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grating structure. The detector is adapted to measure light reflected from the grating structure to generate a reflection profile. The data processing unit is adapted to determine a profile of the interconnect structures based on the reflection profile.

Abstract: Disclosed is a method for removing Pt (or Pt—Ir) and BST contaminants on the surface edge, back, and bevel of a semiconductor wafer. A wafer on which a stacked film selected from the group of a Pt film, a Pt—Ir film, and a Ba—Sr—Ti film is formed is prepared. A chemical containing hydrochloric acid is applied only to the surface edge, back, and bevel of the wafer. The surface edge, back, and bevel of the wafer are rinsed with pure water. Further, a chemical containing hydrogen fluoride is applied. The surface edge, back, and bevel of the wafer are rinsed again with pure water.

Abstract: A method and apparatus for creating objects on a semiconductor wafer includes a mask/reticle having a substantially uniform pattern of features. The wafer is illuminated through the mask/reticle to create a corresponding uniform pattern of objects on the wafer. Selected objects created by the uniform pattern of features are then utilized to provide desired electrical functions on the integrated circuit. In one embodiment of the invention, the objects are interconnect wires formed by a mask or reticle having a substantially uniform pattern of strips that extends over an area of the integrated circuit. Interconnect wires of different lengths are created by defining endpoints on the strips or by exposing areas on the wafer corresponding to the endpoints of the wires.

Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere. After having allowed a silicon dioxide layer with a predetermined thickness to grow on a surface of a silicon crystal, a surface of the silicon dioxide is exposed to organic gas containing no hydroxyl group or is exposed to ammonia gas.

Abstract: A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.

Abstract: A method is provided that comprises forming a first dielectric layer on a workpiece, measuring a thickness of the first dielectric layer, and forming a second dielectric layer above the first dielectric layer, the second dielectric layer being formed to a thickness that is determined based upon the measured thickness of the first dielectric layer.

Abstract: This invention relates to optical metrology tools that are used to evaluate small measurement areas on a semiconductor wafer, where the measurement area is surrounded by a material different from the measurement area. In one embodiment, a probe beam is scanned over the measurement area and the surrounding material as data is taken at multiple locations. A processor determines the characteristics of the measurement area by identifying an extremum value of the measurements which represents the center of the measurement area. In another embodiment, the processor determines the characteristics of the sample using a combination of light measured from within and without the measurement area. The measured data is treated as a combination of light from both regions and mathematically modeled to account for both the contribution of the light reflected from the measurement area and the light reflected from the surrounding material.

Abstract: When tantalum pentoxide film that is deposited on silicon wafer is subjected to a heat treatment in an oxygen atmosphere to improve crystallinity, refractive index is measured by an ellipsometer to appraise change in the crystallinity or change in the relative dielectric constant of the dielectric film and judge the adequacy of the heat treatment temperature. In particular, when the dielectric film is a structure that includes tantalum pentoxide film in which crystallinity is changed by heat treatment and silicon oxide film in which film thickness is changed by heat treatment, the temperature of the heat treatment can be accurately appraised by taking advantage of the correlation between the temperatures of the heat treatment and the refractive indices of the laminated films, this correlation having a curve with a maximum point and a minimum point.

Abstract: The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: Methods and systems are provided for depositing a magnetic film using one or more long throw magnetrons, and in some embodiments, an ion assist source and/or ion beam source. The long throw magnetrons are used to deposit particles at low energy and low pressure, which can be useful when, for example, depositing interfacial layers or the like. An ion assist source can be added to increase the energy of the particles provided by the long throw magnetrons, and/or modify or clean the layers on the surface of the substrate. An ion beam source can also be added to deposit layers at a higher energies and lower pressures to, for example, provide layers with increased crystallinity. By using a long throw magnetron, an ion assist source and/or an ion beam source, magnetic films can be advantageously provided.

Abstract: A titanium nitride film is selectively etched relative to a tungsten film by using as an etchant a solution containing hydrochloric acid and a hydrogen peroxide solution, the molar ratio of the hydrogen peroxide in the hydrogen peroxide solution to hydrogen chloride in the hydrochloric acid being 1/100 or less.

Abstract: A process is disclosed for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control wafer in ion implantation. The process involves the steps of (a) subjecting a feed wafer substantially free of oxide or having less than approximately 4 angstroms of silicon oxide thereon to hydrogen termination of the silicon surface; or (b) subjecting such a feed wafer to said hydrogen termination followed by subjecting the resulting wafer to treatment with an oxidant having a standard reduction potential less than approximately 1.77 volts; the wafer resulting from either step (a) or (b) having a TWO reading less than approximately 30 across the entire wafer.