Abstract: A method of forming a copper dual damascene structure is disclosed. The method comprises forming copper lead lines and copper contacts simultaneously and selectively depositing tungsten layers on silicide layers formed on the active regions to complete the copper dual damascene structure and avoid the diffusion of copper into the active regions.

Abstract: A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.

Abstract: A method for manufacturing a condenser microphone capable of directly bonding an FET chip on each cell of a wafer on the pattern on a printed circuit board, thereby preventing the occurrence of badness by the disconnection of the FET terminals, removing the generation of noise, and achieving the microminiaturization of the product.

Abstract: A fabrication method for a dual damascene structure is described wherein a substrate covered by a HSQ layer is provided. An E-beam curing is conducted on the HSQ layer where the via hole is to be formed. Photolithography and etching are further conducted on the HSQ layer to form a trench. Since the E-beam cured HSQ layer and the thermally cured HSQ layer have a high etching selectively ratio, the HSQ layer that has not been E-beam cured can be wet etched to from a via hole. A dual damascene structure is formed after filling the trench and the via hole with a conductive material, wherein either the via hole or the trench can be first formed.

Abstract: A method includes identifying and determining a position of a scribe grid on a front-side surface of a wafer with a camera. Based on this information, a laser is fired to form an alignment mark on the back-side surface of the wafer. Advantageously, the alignment mark is positioned with respect to the scribe grid to within tight tolerance. The wafer is then cut from the backside surface using the alignment mark as a reference. Of importance, the wafer is cut from the back-side surface thus protecting the front-side surface of the wafer. Of further importance, the wafer is precisely cut such that the scribe line is not fabricated with the extra large width of scribe lines of conventional wafers designed to be cut from the back-side surface.

Abstract: A system for flipping a semiconductor workpiece on its thin edge for microscope inspection of a workpiece facet is disclosed. The system has a holding device attached to a handling block. The holding device picks a workpiece by one of its thin edges. The edge of the workpiece may be attached to the holding device by vacuum. Then an operator rotates the handling block ninety degrees, which in turn rotates the holding device and workpiece ninety degrees. After rotation, one of the workpiece facets faces upward and perpendicular to the microscope for proper inspection of the facet.

Abstract: A method for cleaning the surface of a semiconductor wafer is disclosed. A plasma ashing process is performed on the surface of the semiconductor wafer. The plasma ashing process is performed in a chamber that contains oxygen and carbon tetrafluoride (CF4). An ozone-containing deionized (DI) water cleaning procedure, an amine-based solvent cleaning procedure and a fluoride-based solvent cleaning procedure are then performed to clean the surface of the semiconductor wafer without over-etching the silicon oxide of the street. Finally, an oxygen plasma cleaning process is performed to remove any residual photo-resist.

Abstract: A method is provided for preparing a sample for cross-section analysis by a transmission electron microscope. Semiconductor samples containing recessed portions or unfilled structures are filled with a filling material so as to produce a planar top surface onto which a metal layer can be deposited for thinning the sample to a thickness of less than 100 nm by an FIB technique.

Abstract: Current reactive ion etching (RIE) techniques are not applicable to back side etching of semiconductor devices. According to an example embodiment, the present invention is directed to a method for analyzing a semiconductor device having a back side and a circuit side opposite the back side. An ion gas including SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region is etched using reactive ion etching (RIE). An exposed region is formed, and circuitry in the device is accessed via the exposed region. The use of the ion gas enables back side RIE that is capable of producing an etched surface that is usable for back side access.

Abstract: An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by PCVD, LPCVD or high temperature CVD, forming a SiON or Si-rich SiN ARC on the silicon oxide buffer layer, forming a photoresist mask on the ARC, patterning the underlying silicon layer to form a conductive line or gate electrode, stripping the photoresist mask and then stripping the ARC with hot phosphoric acid while the silicon oxide buffer layer protects the underlying silicon feature from pitting.

Abstract: A chip scale package (CSP) fabricating method is provided. In this method, CSP chips are fabricated on a wafer and subjected to an electric die sorting (EDS) process. Then, CSP chips determined to be non-defective through the FDS process are packaged into a CSP strip. and the CSP strip is subjected to a final test. Then, the CSP strip subjected to the final test is singulated into individual CSPs. Following this, the CSPs are surface-mounted on a module board. Substantially all of the CSPs on the CSP module board are subsequently burn-in tested. As a result, productivity is improved, and manufacturing costs are reduced.

Abstract: A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

Abstract: Application of a potential difference across a doped region formed on an integrated circuit allows management of thermal energy directly on the chip surface. Individual temperature control cells are formed by ion implanting N- and P-type dopant into adjacent regions, and then forming a metal bridge across the similarly positioned ends. Placing a potential drop across metal contacts of the cell changes the temperature of the contacts relative to that of the electrically conducting bridge. Fabrication of arrays of temperature control cells of various shapes and sizes permits extremely precise heating and cooling of specific regions of the integrated circuit. Management of thermal energy on the IC in accordance with the present invention may be enhanced by forming arrays of temperature control cells possessing multiple tiers.

Abstract: This invention relates to ellipsometry and reflectometry optical metrology tools that are used to evaluate semiconductor wafers and is directed to reducing errors associated with material surrounding a desired measurement area or pad, either by minimizing the uncertainties in positioning the measurement beam or by taking into account the effects of the surrounding material in analyzing the measured data. One aspect the present invention utilizes a technique where initially one purposefully aims to place the optical spot of the measurement beam a few microns away from the center of the target pad. Then a series of measurements are made with each measurement separated by a small stage jog as the optical spot is scanned over the measurement pad. Provided the surrounding material is the same on both sides of the pad, one finds that the data invariably has either a cup or inverted “U” shape or an inverted cup or “U” shape when viewed as a function of position.

Abstract: A method of fabricating an infrared detector, a method of controlling the stress in a polycrystalline SiGE layer and an infrared detector device is disclosed. The method of fabricating includes the steps of forming a sacrificial layer on a substrate; patterning said sacrificial layer; establishing a layer consisting essentially of polycrystalline SiGe on said sacrificial layer; depositing an infrared absorber on said polycrystalline SiGe layer; and thereafter removing the sacrificial layer. The method of controlling the stress in a polycrystalline SiGe layer deposited on a substrate is based on varying the deposition pressure. The infrared detector device comprises an active area and an infrared absorber, wherein the active area comprises a polycrystalline SiGe layer, and is suspended above a substrate.

Abstract: A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate, and interconnected by interlevel conductors through the substrate. In the package, the external contacts on a first substrate are bonded to the contact pads on an adjacent second substrate, so that all of the dice in the package are interconnected. The fabrication process includes forming multiple substrates on a panel, mounting the dice to the substrates, stacking and bonding the panels to one another, and then separating the substrates from the stacked panels to form the packages.

Abstract: A wafer-cleaning module is disclosed for removing contaminants from a semiconductor wafer prior to measurement in a metrology tool. The cleaning module includes a heating chamber including a heater plate for heating the wafer by conduction. A separate cooling chamber is provided to cool the wafer. The system is controlled by a processor so the heating cycle, cooling cycle and the time periods between these cycles and the measurement cycle are uniform for all wafers.

Abstract: A method for determining translation portion of misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer in the stepper. In another step a first pattern, including an error-free fine alignment target, is created on the wafer. Next, the wafer is realigned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the translational error between the first pattern and the second pattern is measured.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for testing a flip chip semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For some chips, thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a special test fixture having a heat-dissipating device is arranged to draw heat from the device.