Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric material layer of a semiconductor structure formed on a substrate includes directing a high energy ion beam at a portion of the substrate and sputtering off a plurality of targeted ions from the substrate. The thickness of the dielectric material layer is then determined as a function of a dosage level of the targeted ion and a density of the targeted ion in the dielectric material.

Abstract: The present invention provides for a method and an apparatus for performing automated rework in a manufacturing process. A lot of semiconductor devices is processed using a first set of control input parameters. The first set of control input parameters is stored in a memory location. Process data from the processing of the lot of semiconductor devices is acquired. Errors in the process data are analyzed. At least one automated rework procedure is performed on the lot of semiconductor devices in response to the analysis of the process data.

Abstract: An adjustment error in a photolithographic stepping printer is detected by applying photoresist to a semiconductor wafer, and exposing the wafer to substantially identical light images in multiple locations using a stepping printer. The light images are defined by an optical reticle and include a plurality of lines or other features that are spaced from each other at approximately the resolution limit of the printer. Developer (16) is applied to the wafer to produce visible images corresponding to the light images. The visible images function as diffraction gratings which reflect light from the wafer. The visible images are inspected optoelectronically or manually. An adjustment error is determined to exist if the visible images appear substantially identical but are uneven or otherwise abnormal.

Abstract: Visible defects are detected on a process semiconductor wafer. Defects are classified according to appearance and an association is kept between classes and apparatuses. When the density of defects in a given class exceeds a control limit the associated apparatus is switched off-line. In an embodiment, the same wafer is inspected repeatedly, each time after a different processing steps and information about the location of detected defects is kept. Defects which occur at a location where defects have already been detected in a previous inspection after an earlier processing step are eliminated from the density which is compared to the control limit.

Abstract: A method is provided for manufacturing, the method including processing a workpiece in a processing step and detecting defect data after the processing of the workpiece in the processing step has begun. The method also includes filtering the defect data using a fractal filter and forming an output signal corresponding to at least one type of defect based on the fractally filtered defect data. The method further includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.

Abstract: A method for characterizing a structure including single-crystal silicon-germanium areas on a single-crystal silicon substrate, including the steps of measuring the X-ray diffraction spectrum of the structure, simulating the diffraction spectrum of a single-crystal silicon substrate, simulating the diffraction spectrum of a single-crystal silicon substrate entirely coated with a single-crystal SiGe layer, adding the simulated spectrums while assigning them weights a and 1-a to obtain a sum spectrum, comparing the sum spectrum with the measured spectrum and adjusting the simulation parameters and weight a to reduce the distance between the sum spectrum and the measured spectrum, and after optimizing, adopting the simulation parameters as the measurement parameters.

Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: In order to form a self-aligned damascene gate with an attendant contact or contacts, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. This dielectric layer is polished for planarity, a combined gate and contact mask is used to pattern the dielectric, and the interlayer dielectric is etched and the resist is stripped. The gate dielectric is deposited and polysilicon is then deposited over the dielectric and doped by implantation and then annealed. This polysilicon layer is polished to the dielectric level. The wafer is then masked to cover the gate and the polysilicon is anisotropically etched off in the contact areas. The exposed polysilicon at the gate site and the silicon exposed at the contact site are then salicided.

Abstract: A multi-level registration control system for a photolithography process includes a photolithography device that prints first, second and third layers on a wafer. A first overlay mark defines overlay errors in a first direction between the first and third layer. The first overlay mark also defines overlay errors between the second and third layers. An overlay measurement device measures the overlay errors and generates an overlay signal. A feedback controller is connected to the overlay measurement device and the photolithography device. The feedback controller receives the overlay error signal and generates and transmits an alignment correction signal to the photolithography device. The first overlay mark is a box-in-box overlay mark or a frame-in-frame overlay mark. By providing a single overlay mark to align three layers, the multi-layer overlay control system reduces scribe grid area and saves useful silicone surface area.

Abstract: An apparatus for the fabrication of a semiconductor assembly and a method of underfilling flip-chip devices are disclosed. The apparatus for multiple controlled dispensing of polymeric precursors filled with silica and anhydrides comprises a center feed tube supplying the proecursor; a header connecting the center tube to a plurality of distribution tubes, whereby the distribution tubes acquire predetermined distances from the center tube; a nozzle at the end of each distribution tube; and these nozzles having increasingly larger cross sections, the farther the respective distribution tube is positioned from the center tube, whereby the dispense rate of the precursor remains the same for all distribution tubes.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then depositing an ultra-thin nitride film on the base film. The semiconductor device is then annealed in situ in ammonia, following which the device is oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator, and the gates are next implanted with Nitrogen to passivate dangling Nitrogen and Silicon bonds in the nitride, thus decreasing the charge content in the film. Consequently, the resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: A method of manufacturing semiconductor devices wherein defect images are isolated from reference images in an optical tool. Each layer of a semiconductor are inspected for defects and identified defect images are subtracted from reference images providing an operator of the optical tool a resultant image of the defects or a highlighted image of the defect.

Abstract: In a field effect transistor, an Si1-xGex layer is provided between a source or drain electrode deriving region and a corresponding metal (interconnection) electrode or between a contact deriving region and a metal layer formed on the upper portions of the contact deriving region to form an ohmic contact to thereby prevent the aluminum metal layer from penetrating into a p-n junction and to reduce a contact resistance.

Abstract: Resin meltable at a time of reflowing is provided on the surface of a semiconductor chip and top ends of the connection electrodes are located parallel with the surface of the resin. A semiconductor chip is mounted on a mounting substrate and, upon reflowing, the resin is molten to allow the semiconductive chip to be bonded to the mounting substrate and encapsulate a resultant structure.

Abstract: A memory cell for a dynamic random access memory includes a pass transistor and a storage capacitor. The transistor is a vertical transistor formed along an upper portion of a sidewall of a polysilicon-filled trench in a monocrystalline silicon body with the source and drain in the body and the source contact, gate and gate contact in the trench, with its gate dielectric being an oxide layer on the sidewall portion of the trench. The capacitor is a vertical capacitor formed along a deeper portion of the trench and has as its storage plate a lower polysilicon layer in the trench and as its reference plate a deep doped well in the body. The source contact and the storage plate are in electrical contact in the trench and the source contact and the gate contact are in the trench electrically isolated from one another.