Patents Examined by Pamela E Perkins
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Patent number: 9275853Abstract: Embodiments of the disclosure generally relate to methods of adjusting transistor flat band voltage, and transistor gates formed using the same. In one embodiment, a method sequentially includes cleaning a substrate, annealing the substrate in a nitrogen-containing environment to form silicon-nitrogen bonds, hydroxylating the substrate surface, and depositing a hafnium oxide layer over the substrate. In another embodiment, the method further includes depositing an aluminum oxide layer over the substrate prior to depositing the hafnium oxide layer, and then annealing the substrate.Type: GrantFiled: July 28, 2014Date of Patent: March 1, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Tatsuya Sato, Steven C. H. Hung, Eran Newman
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Patent number: 9276115Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure.Type: GrantFiled: August 29, 2013Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventor: Effendi Leobandung
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Patent number: 9276237Abstract: An object of the present invention is to provide a method for an organic EL element in which the organic EL element can be readily produced by a roll to roll method, in the case where the respective components of the organic EL element are sequentially laminated from a cathode. A method for manufacturing an organic EL element of a preferable embodiment is a method for manufacturing an organic EL element by laminating, on a supporting substrate, a cathode, an electron injection layer, a light-emitting layer and an anode to manufacture an organic EL element by a roll to roll method, the manufacturing method including a step for forming an electron injection layer on the cathode of the supporting substrate on which the cathode has been formed, by applying an ink including an ionic polymer so as to form a film, a step for forming a light-emitting layer on the electron injection layer, and a step for forming an anode on the light-emitting layer.Type: GrantFiled: July 20, 2011Date of Patent: March 1, 2016Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventor: Shoji Mima
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Patent number: 9275912Abstract: Methods for quantifying extended defects in a gallium-containing nitride crystal, wafer, or device, are disclosed. The methods include providing a gallium-containing nitride crystal, wafer, or device, processing the gallium-containing nitride crystal, wafer, or device in an etchant solution comprising one or more of H3PO4, H3PO4 that has been conditioned by prolonged heat treatment to form polyphosphoric acid, and H2SO4; removing the gallium-containing nitride crystal, wafer, or device from the etchant solution; and quantifying the concentration of at least one of etch pits or etch grooves.Type: GrantFiled: August 29, 2013Date of Patent: March 1, 2016Assignee: Soraa, Inc.Inventors: Wenkan Jiang, Dirk Ehrentraut, Bradley C. Downey, Mark P. D'Evelyn
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Patent number: 9276043Abstract: A method of manufacturing a photoelectric conversion device includes: forming a first electrode on a first surface side of a substrate that has two opposing surfaces; forming an electrode section on a second surface side of the substrate, the electrode section being used for external connection; and after forming the first electrode and the electrode section, forming an organic photoelectric conversion layer and a second electrode on the first electrode.Type: GrantFiled: January 18, 2013Date of Patent: March 1, 2016Assignee: SONY CORPORATIONInventors: Nobutoshi Fujii, Hayato Iwamoto
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Patent number: 9269891Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a āZā axis magnetic field onto sensors orientated in the XY plane.Type: GrantFiled: August 21, 2013Date of Patent: February 23, 2016Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
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Patent number: 9269575Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.Type: GrantFiled: October 1, 2013Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz
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Patent number: 9263419Abstract: A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames.Type: GrantFiled: August 30, 2013Date of Patent: February 16, 2016Assignee: Infineon Technologies AGInventors: Nee Wan Khoo, Lay Yeap Lim
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Patent number: 9260654Abstract: Disclosed is a manufacturing method for a light emitting device including a light emitting element and a wavelength converting part which converts light emitted from the light emitting element into light of another wavelength. The manufacturing method includes a first step and a second step. The first step is a step of applying onto the light emitting element and drying a first liquid mixture in which phosphor and plate-like particles are dispersed in polyhydric alcohol having a valence of two or more to form a phosphor layer. The second step is a step of applying onto the phosphor layer and firing a second liquid mixture in which a translucent ceramic precursor is dispersed in a solvent to form the wavelength converting part.Type: GrantFiled: February 15, 2012Date of Patent: February 16, 2016Assignee: KONICA MINOLTA, INC.Inventors: Takashi Washizu, Takuji Hatano, Yoshihito Taguchi
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Three dimensional NAND device with birds beak containing floating gates and method of making thereof
Patent number: 9252151Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.Type: GrantFiled: February 18, 2014Date of Patent: February 2, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis -
Patent number: 9252235Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.Type: GrantFiled: August 2, 2013Date of Patent: February 2, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Donghyun Roh, Pankwi Park, Dongsuk Shin, Chulwoong Lee, Naein Lee
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Patent number: 9252319Abstract: Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer.Type: GrantFiled: June 12, 2014Date of Patent: February 2, 2016Assignee: SunPower CorporationInventors: Paul Loscutoff, David D. Smith, Michael Morse, Ann Waldhauer, Taeseok Kim, Steven Edward Molesa
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Patent number: 9252324Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.Type: GrantFiled: May 30, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INCInventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 9252017Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.Type: GrantFiled: October 2, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9252016Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.Type: GrantFiled: September 4, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9252043Abstract: A film deposition method is provided. A first metal compound film is deposited by performing a first cycle of exposing a substrate to a first source gas containing a first metal, and of exposing the substrate to a reaction gas reactive with the first source gas. Next, the first source gas is adsorbed on the first metal compound film by exposing the substrate having the first metal compound film deposited thereon to the first source gas. Then, a second metal compound film is deposited on the substrate by performing a second cycle of exposing the substrate having the first source gas adsorbed thereon to a second source gas containing a second metal, and of exposing the substrate to the reaction gas reactive with the second source gas.Type: GrantFiled: July 8, 2013Date of Patent: February 2, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Hiroaki Ikegawa, Masahiko Kaminishi, Jun Ogawa
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Patent number: 9252083Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.Type: GrantFiled: February 10, 2015Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
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Patent number: 9252014Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.Type: GrantFiled: September 4, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz
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Patent number: 9252566Abstract: A method of manufacturing a light emitting element includes, sequentially, (a) forming a mask layer for selective growth; (b) forming a layered structure body by layering a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (c) forming, on the second surface of the second compound semiconductor layer, a second electrode and a second light reflecting layer formed from a multilayer film; (d) fixing the second light reflecting layer to a support substrate; (e) removing the substrate for manufacturing a light emitting element, and exposing the first surface of the first compound semiconductor layer and the mask layer; and (f) forming a first light reflecting layer formed from a multilayer film and a first electrode on the first surface of the first compound semiconductor layer.Type: GrantFiled: August 1, 2014Date of Patent: February 2, 2016Assignee: SONY CORPORATIONInventors: Noriyuki Futagawa, Tatsushi Hamaguchi, Masaru Kuramoto
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Patent number: 9245972Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.Type: GrantFiled: September 3, 2013Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Yuan-Chi Pai, Fong-Lung Chuang