Patents Examined by Pamela E Perkins
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Patent number: 9324705Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: GrantFiled: January 22, 2014Date of Patent: April 26, 2016Assignee: MEDIATEK INC.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Patent number: 9318328Abstract: A method of forming a silicon film includes a first film forming process, an etching process, a doping process, and a second film forming process. In the first film forming process, a silicon film doped with impurities containing boron is formed so as to embed a groove provided on an object to be processed. In the etching process, the silicon film formed in the first film forming process is etched. In the doping process, the silicon film etched in the etching process is doped with impurities containing boron. In the second film forming process, a silicon film doped with impurities containing boron is formed so as to embed the silicon film that is doped in the doping process.Type: GrantFiled: May 24, 2013Date of Patent: April 19, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Katsuhiko Komori, Akinobu Kakimoto, Mitsuhiro Okada, Nobuhiro Takahashi
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Patent number: 9318728Abstract: A manufacturing method for an organic light-emitting element includes: a first step of forming a first electrode, and forming an organic layer including a light-emitting layer; a second step of forming a second electrode, and thereby forming an element structure including the first electrode, the organic layer, and the second electrode; and a third step of performing an aging process by applying electric power between the first electrode and the second electrode in the element structure. a duration of the application of electric power in the third step is determined as the time elapsed before a time point at which a rate of decrease in a luminance of the light-emitting layer is substantially equal to a rate of decrease in a luminance of the element structure.Type: GrantFiled: May 27, 2011Date of Patent: April 19, 2016Assignee: JOLED INC.Inventor: Masaki Aonuma
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Patent number: 9318697Abstract: In a method of detecting an etch by-product, the method including forming a magnetic layer including palladium (Pd) on a substrate; etching the magnetic layer to form a magnetic layer pattern; depositing a mixture including an alkyl bromide compound on a surface of the magnetic layer pattern; and measuring a current difference between the substrate and the mixture to detect an etch by-product on the surface of the magnetic layer pattern.Type: GrantFiled: August 1, 2014Date of Patent: April 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Hye Bae, Won-Jun Lee, Sung-Yoon Chung, Taek-Dong Chung
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Patent number: 9318525Abstract: A first pixel includes a first charge accumulation portion of a first conductivity type in a first region. A second pixel includes a second charge accumulation portion of the first conductivity type in a second region and a semiconductor region of a second conductivity type in a third region. Impurities of the second conductivity type are doped in the third region and the impurities of the second conductivity type are doped in at least the second region to generate a first difference between quantities of doping the impurities of the second conductivity type in the first and second regions. Impurities are doped in the first and second regions to reduce a second difference, caused by the first difference, between net quantities of doping impurities of the first conductivity type in the first and second regions.Type: GrantFiled: August 1, 2014Date of Patent: April 19, 2016Assignee: Canon Kabushiki KaishaInventor: Hideyuki Itoh
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Patent number: 9318447Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.Type: GrantFiled: July 18, 2014Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
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Patent number: 9312227Abstract: A method of joining semiconductor substrates, which may include: forming an alignment key on a first semiconductor substrate; forming an insulating layer on the first semiconductor substrate and the alignment key; forming a first metal layer pattern and a second metal layer pattern on the insulating layer; forming a first protrusion and a second protrusion, and an alignment recess positioned between the first protrusion and the second protrusion on a second semiconductor substrate; forming a third metal layer pattern and a fourth metal layer pattern on the first protrusion and the second protrusion, respectively; and joining the first semiconductor substrate and the second semiconductor substrate, in which the alignment key is positioned at the alignment recess when the first semiconductor substrate and the second semiconductor substrate are joined, is provided.Type: GrantFiled: July 29, 2014Date of Patent: April 12, 2016Assignee: Hyundai Motor CompanyInventors: Ilseon Yoo, Hiwon Lee, Soon-myung Kwon, Hyunsoo Kim
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Patent number: 9312480Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.Type: GrantFiled: July 3, 2014Date of Patent: April 12, 2016Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Sumeet C. Pandey
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Patent number: 9312344Abstract: A method includes annealing a silicon region in an environment including hydrogen (H2) and hydrogen chloride (HCl) as process gases. After the step of annealing, a semiconductor region is grown from a surface of the silicon region.Type: GrantFiled: May 15, 2013Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Christopher Holland, Georgios Vellianitis
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Patent number: 9312169Abstract: Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.Type: GrantFiled: August 7, 2014Date of Patent: April 12, 2016Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Christophe Bouvier, Gabriel Pares
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Patent number: 9305846Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.Type: GrantFiled: January 19, 2015Date of Patent: April 5, 2016Assignees: GlobalFoundries Inc., International Business Machines Corporation, Renesas Electronics CorporationInventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Steven Bentley, Toshiharu Nagumo, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
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Patent number: 9306110Abstract: Apparatuses and methods for synthesizing nanoscale materials are provided, including semiconductor nanowires. Precursor solutions include mixed reagent precursor solutions of metal and chalcogenide precursors and a catalyst, where such solutions are liquid at room temperature. The precursor solutions are mixed by dividing a solution flow into multiple paths and converging the paths to form a uniform solution. A thermally controlled reactor receives the uniform solution to form semiconductor nanowires. Various electronic, optical, and sensory devices may employ the semiconductor nanowires described herein, for example.Type: GrantFiled: July 29, 2014Date of Patent: April 5, 2016Assignee: US Nano LLCInventors: Anthony C. Onicha, Louise E. Sinks, Stefanie L. Weber
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Patent number: 9305922Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.Type: GrantFiled: February 27, 2015Date of Patent: April 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ju-Youn Kim
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Patent number: 9305937Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.Type: GrantFiled: October 21, 2014Date of Patent: April 5, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
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Patent number: 9299841Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure.Type: GrantFiled: September 11, 2013Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventor: Effendi Leobandung
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Patent number: 9299562Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.Type: GrantFiled: December 13, 2013Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 9293369Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.Type: GrantFiled: May 12, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 9276172Abstract: It is provided a method of manufacturing a display device for which the damage caused to the display panel due to processing at high temperatures is reduced. The method of manufacturing a display device includes: preparing a carrier substrate including a surface treated region; laying a mother substrate on the carrier substrate; progressing a process of forming a thin film on the mother substrate; and separating the carrier substrate from the mother substrate by using the surface treated region as an initial separation point. Bonding is formed between the carrier substrate and the mother substrate during forming the thin film over the areas that are not surface treated. The two substrates may be separated by disposing permeating oil on the surface treated region wherefrom oil permeates through the remaining regions by osmotic pressure. This way damage caused to the display panel during thin film processing is reduced.Type: GrantFiled: July 22, 2013Date of Patent: March 1, 2016Assignee: Samsung Display Co., Ltd.Inventors: Jong Hwan Lee, Young Bae Kim, Jong Seong Kim, Tae Hwan Kim, Myeong Hee Kim, Woo Jae Lee
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Patent number: 9275890Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.Type: GrantFiled: March 15, 2013Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy C. Wei, Jeong Soo Kim, Francis M. Tambwe
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Patent number: 9275902Abstract: Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.Type: GrantFiled: March 26, 2014Date of Patent: March 1, 2016Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar