Patents Examined by Parshotam S. Lall
  • Patent number: 6170997
    Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: January 9, 2001
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Larry M. Mennemeier, Alexander D. Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrik Lin, Romamohan R. Vakkalagadda
  • Patent number: 6118936
    Abstract: A signaling network management system (SNMS) collects network topology, traffic, performance and fault information, correlates that information and displays the information to system operators. It includes a distributed client/server platform that receives and processes information relating to network events that is generated by various signaling network elements. Each network event is parsed and formatted to a standardized format to allow processing of events generated by any type of element. The formatted events are correlated and displayed to system operators. Correlation of the different types of events is performed using programmable analysis rules. The system also correlates signaling network events with transmission alarms and network maintenance schedule information. This allows the system operators to account for outages due to transmission events, such as fiber cuts, and to network maintenance. It also allows operator to worn maintenance personnel of maintenance impacting events.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: September 12, 2000
    Assignee: MCI Communications Corporation
    Inventors: Douglas Gerard Lauer, Michael Robert Smith
  • Patent number: 6115545
    Abstract: A network device connected to a local network is configured using a module operating within a console connected to the local network. Once activated, the module obtains an unused network address. After obtaining the unused network address, the console waits for receipt of a request from the network device. Upon receipt of the request, the console forwards to the network device a response. The response includes the unused address along with subnet and gateway information for the console. The console then establishes a network connection to the network device and displays on a monitor for the console, an address value, a subnet mask value and a gateway value for the network device.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: September 5, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Peter E. Mellquist
  • Patent number: 6085261
    Abstract: A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion of the burst transaction. The present invention offers a method of terminating a burst transaction without the addition of wait states, and further allows termination to effectively interrupt the burst transaction rather than waiting for burst completion. In one embodiment, on the negation of a burst request signal during a burst transfer, external bus interface (30) terminates the burst transfer without waiting for the completion of the burst transaction.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: July 4, 2000
    Assignee: Motorola, Inc.
    Inventors: Kenneth L. McIntyre, Jr., Kirk Livingston, Daniel W. Pechonis, Anthony M. Reipold
  • Patent number: 6072942
    Abstract: A system and method for filtering electronic mail messages is described. A message is received an processed through a one or more filter flows. Each filter flow is comprised of one or more self-contained nodes which can be combined in whatever order is required to enforce a given security policy. Node independence provides a policy-neutral environment for constructing filter flows. A filter flow may be as simple as forwarding the mail to the intended recipient, or may perform one or more checks where it decides whether to forward, reject, return (or some combination thereof) the message. Certain node types are also able to append information on to a mail message, while others are able to modify certain parts of a mail message. Several of the node types are able to generate audit or log messages in concert with processing a mail message.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: June 6, 2000
    Assignee: Secure Computing Corporation
    Inventors: Edward B. Stockwell, Paula Budig Greve
  • Patent number: 6064805
    Abstract: A method, system, and computer program product specifies a communication intraconnect architecture that supports a pull model based data communication where data is sent to a receiver along with a memory address (a receiver buffer address or a reference to a pool manager or buffer pool) where the data is to be stored. CIA primitives are used to create nodes and dialog objects managed by send and receive IFEs. A logical dialog is established between corresponding send and receive dialog objects. A send dialog object includes a reference that identifies for the send IFE the corresponding receive dialog object in the receive IFE. The receive dialog object includes a reference that identifies for the receive IFE the corresponding send dialog object in the send IFE. Receive and send primitives are used to provide pull model data communication over a logical dialog. Receive with Buffer and Receive with Buffer Pool operations are provided.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: May 16, 2000
    Assignee: Unisys Corporation
    Inventors: Duane J. McCrory, Jerry S. Bassett, Mark S. Brandt, Robert A. Johnson, James J. Leigh, Robert K. Moulton
  • Patent number: 6049866
    Abstract: A method and a system for fast user mode cache synchronization. The present invention is implemented on a computer system having a instruction cache. The system of the present invention detects a simulated instruction from a process running on the computer system while the process is running in a user mode. The simulated instruction causes an error exception and the operating system traps the error. The kernel then interprets the simulated instruction is then as an instruction cache synchronization instruction. The instruction cache synchronization instruction is executed and the program counter is incremented. The present invention then returns to the process in user mode. During instruction execution, preloaded registers that contain a starting address and an ending address, defining an address range, are read. The entries of the instruction cache are read and those entries falling within the address range are marked as invalid to maintain instruction cache coherency.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: April 11, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: William J. Earl
  • Patent number: 6044205
    Abstract: An automated communications system operates to transfer data, metadata and methods from a provider computer to a consumer computer through a communications network. The transferred information controls the communications relationship, including responses by the consumer computer, updating of information, and processes for future communications. Information which changes in the provider computer is automatically updated in the consumer computer through the communications system in order to maintain continuity of the relationship. Transfer of metadata and methods permits intelligent processing of information by the consumer computer and combined control by the provider and consumer of the types and content of information subsequently transferred. Object oriented processing is used for storage and transfer of information.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: March 28, 2000
    Assignee: Intermind Corporation
    Inventors: Drummond Shattuck Reed, Peter Earnshaw Heyman, Steven Mark Mushero, Kevin Benard Jones, Jeffrey Todd Oberlander, Dan Banay
  • Patent number: 6035118
    Abstract: A technique for eliminating the performance penalty of implementing jump instructions in a deeply pipelined processor includes a pipeline having a signal for indicating that the top of the address return stack has been updated by an address moved to the return register. An instruction moving a previously computed jump target address to the return register is included in code to be executed. The pipeline uses the instruction at the top of the RAS as a guess of the target instruction of a fetched jump instruction and immediately begins fetching instructions indicated by the guess.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: March 7, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Gary Lauterbach, Kit Tam
  • Patent number: 6006030
    Abstract: A microprocessor includes a programmable instruction trap that can be used to deimplement instructions that lead to erroneous results. Upon discovery of a logic design defect, a microprocessor manufacturer can distribute an updated exception handler and a patch for a boot sequence. Upon power up, the boot sequence programs instructions to be deimplemented into a trap list. Each received instruction (issued by an application program, for example) not matching any listed instruction is executed in due course. When it matches a listed deimplemented instruction, the received instruction is trapped: it is not executed but is stored in a dedicated register. An exception handler is called that can examine the trapped instruction and substitute a suitable routine. If the trapped instruction is conditionally deimplemented and the problematic conditions do not pertain, the exception handler can reissue the instruction after temporarily deactivating the trapping function.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: December 21, 1999
    Assignee: VLSI Technology, Inc.
    Inventor: Kenneth A Dockser
  • Patent number: 6003122
    Abstract: An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration.A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: December 14, 1999
    Assignee: Intel Corporation
    Inventors: Mark A. Yarch, Byron R. Gillespie
  • Patent number: 6000028
    Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: December 7, 1999
    Assignee: Digital Equipment Corporation
    Inventors: Anton Chernoff, John S. Yates
  • Patent number: 5974518
    Abstract: Disclosed is a network device having a shared memory, a controller for storing Ethernet frames in frame buffers using data chaining to divide up at least the larger frames over a plurality of same sized buffers in the shared memory, wherein there is a tradeoff between using 1) larger buffers capable of receiving more of or all of the larger frames (more wasted buffer space) or 2) smaller buffers requiring more data chaining (wastes processing time to reassemble the frames) and an Ethernet driver having a buffer size adaptation routine which uses an algorithm to dynamically size the buffers.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: October 26, 1999
    Assignee: Milgo Solutions, Inc.
    Inventor: Christopher I. Nogradi
  • Patent number: 5974240
    Abstract: In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Following the execution of the condition register modifying instruction, condition register data is set in the condition register rename buffer to reflect the result of such instruction execution. Additionally, an indicator is set to indicate the condition register data is valid. At the time for completing the condition register modifying instruction, the condition register data is transferred from the condition register rename buffer to the architected condition register, thereby permitting condition register modifying instructions to be dispatched, executed, and finished before the condition register is available to complete each condition register modifying instruction.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 26, 1999
    Assignee: International Business Machines Corporation
    Inventor: Kin Shing Chan
  • Patent number: 5974539
    Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: October 26, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Karl M. Guttag, Keith Balmer, Robert J. Gove, Christopher J. Read, Jeremiah E. Golston, Sydney W. Poland, Nicholas Ing-Simmons, Phillip Moyse
  • Patent number: 5966509
    Abstract: A network management device for managing a plurality of network elements has a network element management data acquisition unit for acquiring, in stages, various management data possessed by the network elements when a session with a network element is resumed and when the network management device itself is started up, a rule management table for storing a dependence relationship between an operation and management data necessary to execute the operation, a feasible operation decision processing unit which, when an operation has been specified, refers to the dependence relationship to determine whether management data necessary to execute the operation has been acquired. If the necessary management data has been acquired, a network management execution unit executes network management conforming to the operation.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: October 12, 1999
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Abe, Takahiro Miyazaki, Yuki Kajitani, Kazuya Jimbo, Hideyuki Chiba
  • Patent number: 5961635
    Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: October 5, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Karl M. Guttag, Keith Balmer, Robert J. Gove, Christopher J. Read, Jeremiah E. Golston, Sydney W. Poland, Nicholas Ing-Simmons, Phillip Moyse
  • Patent number: 5963720
    Abstract: A system and method for expediting data processing in a computer system including a network controller and a driver is disclosed. The method and system first provide a hardware structure. The hardware structure has a first plurality of fields and corresponds to a second structure. The second structure has a second plurality of fields. The first plurality of fields of the hardware structure has at least one field more than the second plurality of fields. The method and system then allow the driver to utilize the at least one extra field for increasing efficiency of data processing.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: October 5, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Leonid Grossman
  • Patent number: 5960174
    Abstract: A communications network is used to couple weld controllers and different operator interface units together, regardless of their data structures. An arbitration system provides a means for one operator interface unit to communicate to a selected weld controller at a given period of time. The operator interface units have one of three modes of operation. These include database master, primary master, and secondary master. During setup of the communications network, the master devices are assigned a physical address that defines the its type and priority within the network. The database master is the only device which can automatically download data to a weld controller. It has the highest priority as a network arbiter. The primary master will act as the network abitrator in the absence of a database master. A secondary master must listen for an access grant from the current network arbiter, before initiating a message packet on the network.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: September 28, 1999
    Assignee: Square D Company
    Inventor: Larry A. Dew
  • Patent number: 5953513
    Abstract: The recording and reproducing apparatus comprises an Small Computer System Interface (SCSI) controller, an optical disc device, a magnetic disc device, a disc controller which controls the optical disc device and the magnetic disc device, connectors which connects directly the optical disc device and the magnetic disc device, and a selector which selects one of the optical disc device and the magnetic disc device. A Copy or Verify command is carried out within the apparatus without an SCSI bus, and data are transferred through the connector. Therefore occupation of the SCSI bus and overhead of the SCSI protocol are eliminated, and the apparatus is miniaturized by common use of the SCSI controller and the disc controller.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Eisaku Saiki, Takashi Oeda, Shoichi Miyazawa, Kazuo Shigematsu, Yasunori Kaneda