Abstract: A system for establishing anonymous communications includes a plurality of party terminals, a plurality of requester terminals, and a central controller. The system receives and stores party data about respective parties. Upon receiving criteria for parties of interest from a requestor terminal and authorization from respective parties, the central controller releases to the requester party associated with the parties. The system also establishes communications channels between parties and the requester, while maintaining their anonymity.

Abstract: A parallel local area network server is capable of sharing data and routing messages between workstations in a local area network. An apparatus according to the invention includes a plurality of processing nodes, each constituted by at least a single data processor, and an interconnect by which the processing nodes communicate. A plurality of mass storage devices are associated with the processing nodes, and a plurality of workstation computers are connected to the processing nodes. Each processing node includes is adapted to route messages to workstation computers associated with other processing nodes and to access data located both locally and at data storage devices associated with other processing nodes. A method according to the invention includes receiving a message at a first processing node and determining if the message is directed to a workstation computer at a second processing node and sending the message to the second processing node for subsequent delivery to the workstation computer.

Abstract: A system for facilitating employment searches using anonymous communications includes a plurality of party terminals, a plurality of requestor terminals, and a central controller. The system receives and stores employment data about prospective employment candidates. Upon receiving criteria for candidates of interest from an employer and authorization from the candidates, the central controller releases to the employer the employment data associated with the candidates. The system also establishes communications channels between the employer and the candidates, while maintaining their anonymity.

Abstract: In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

Abstract: A method and apparatus provide for monitoring an auto-negotiation process. A number of intermediate steps in the auto-negotiation process are monitored. A plurality of codes are successively stored in a progress memory to indicate a degree of completion of the auto-negotiation process.

Abstract: A memory control circuit in a CD-ROM driving system is provided which controls the writing and reading of data to and from a memory in accordance with a plurality of data operations. The circuit contains a plurality of requesters, a priority level determiner, and a memory control signal generator. The requesters correspond to the plurality of data operations and respectively generate request signals. Furthermore, the requesters respectively generate physical addresses of the memory which are respectively accessed during the data operations. The priority level determiner determines the priority levels of the request signals and outputs a selection signal based on the request signals and the priority levels. Moreover, the selection signal identifies one of the data operations as a selected data operation. The memory control signal generator generates a memory control signal and a memory address which corresponds to one of the physical addresses to be accessed during the selected data operation.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit.

Abstract: An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register.

Abstract: Software procedure call overhead, i.e. the memory references or other steps taken to save and restore callee save register values during execution of a called procedure, are reduced by restructuring the procedure code during optimization so that unnecessary or redundant save and restore operations are less likely. The procedure exit block is split into first and second exit blocks, with control flow from the first to the second exit block, and return to the calling procedure from the latter. "Shortcut" control paths are directed to the second exit block, while the new, first exit block is used to post-dominate sections of the code not otherwise amenable to shrink-wrapping techniques. Save and restore operations are wrapped around the non-shortcut code and the new exit block. During execution of the procedure as modified, shortcut paths to the second exit block effectively bypass the first exit block, thereby reducing overhead associated with callee save registers referenced in the non-shortcut path.

Abstract: A computer-based method of innovatively solving one or more problems using a group assembled at a computerized meeting. One participant of the group is the client who is the owner of or is responsible for the problem or opportunity to be resolved. Each participant is provided with a computer which is networked with all other computers. A group list is created of all the participants of the group, and one participant is designated the facilitator who controls the problem solving process of the meeting. The remaining participants are designated as resources. An agenda is created consisting of placeholders and activities. The resources enter creative springboards into their computers based on the problem to be solved, and these springboards are distributed to all participants. Builds and elaborations are generated by the resources based on the springboards and distributed to all participants.

Abstract: A system and method of configuring VLANs of a multiple port bridging device by merging potentially conflicting VLANs. One or more VLANs are first defined by the user, and equivalent and subset VLANs are merged. The spanning tree procedure is then performed to determine a root identifier and a root port for each VLAN. The root identifier of each VLAN is compared with the other VLANs, and if equal, the root ports of the two VLANs are compared. If the root identifiers are the same and if the root ports are different for any two VLANs, the two VLANs are merged into a new VLAN. To merge two VLANs, all of the ports of both VLANs are combined to define a new VLAN. Preferably, each VLAN is compared with every other VLAN in this manner. The spanning tree procedure is then executed for the new VLAN, which is then compared to the other VLANs in the same manner.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instructions results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. The line of storage remains allocated until each instruction within the line is ready to retire, and then the line is deallocated as the one or more instructions are concurrently retired.

Abstract: Disclosed is a personal computer system that includes a media console coupled to a system unit with a multi-conductor cable. The media console includes a direct access storage device having an opening for receiving a removable storage medium. The system unit is separate from the console and includes a microprocessor coupled to a local bus and an expansion bus, a non-volatile storage device coupled to the local bus and a power supply for supplying power to the system. The cable has one end coupled to the console and another end coupled to the system unit for electrically connecting devices in the console to devices in the system unit. The system unit has a first interface coupled to the expansion bus and the cable, and the console has a second interface coupled to the cable and the direct access storage device in the console.

Abstract: An improved method and system for accessing the most recent version of a requested data file that has been downloaded into a private network from a source external to the private network. The objects of the method and system are achieved as is now described. A network of computers is defined as private relative to one or more other networks of computers. More than one computer within said defined private network is specified as composing a "common cache." A copy of any data file entering the defined private network from a source external to the defined private network is cached at one or more computers which compose the defined "common cache." In response to a request from a computer within the defined private network for a specific data file which originates from a source external to the defined private network, a determination is made as to whether a copy of the requested specific data file is resident within the defined "common cache.

Abstract: When a data write request is received from an application program, the received data write request is issued to a disk (primary) without waiting next check point, and the data write request is issued to a disk (shadow) after obtaining next check point. When restarting a process from obtained preceding check point, data in the disk (primary) is recovered by data in the disk (shadow). As a result, a delay of I/O request by a check point is decreased, thereby remarkably improving system performance in a normal operation.

Abstract: A system is disclosed that integrates through a single client application access to information resources from a proprietary online service and the Internet. Using a single Web-based client, subscribers enter selections regarding the type of information they would like to retrieve. Relevant information is retrieved from the Internet using the Uniform Resource Locator (URL) addressing scheme of the Internet to locate information on the Internet. Relevant information is retrieved from the online service using extensions to the URL addressing scheme. The extensions map to a proprietary protocol used to obtain information resources from the online service. The client application understands the URLs and extended URLs and manages presentation of the information regardless of the source. Using the present invention, subscribers to online services are no longer required to toggle between a Web browser and service provider communication software in order to view content from both locations.

Abstract: A boosting control method and control apparatus boosts an execution timing of an instruction to be executed as the result of the execution of a branch instruction without a need to wait for the execution of the branch instruction. A boosting control instruction that represents the position of a boosted instruction is placed in an instruction sequence including the boosted instruction. When the instruction sequence including the boosting control instruction is executed, the execution state of a boosted instruction that is represented by the boosting control instruction placed before the branch instruction corresponding to the execution result in the instruction sequence and that is executed before the branch instruction is controlled.

Abstract: A method of effecting a matrix transpose operation in a computer is described. The method uses a computer instruction which restructures a data string by retaining first and last sub-strings of the data string in unchanged positions and interchanges the position of at least two intermediate sub-strings. The data string is formed from sub-strings each representing one or more data value in a matrix.The computer instruction can be effected in a single register store having a predetermined bit capacity addressable by a single address, or in a pair of such register stores.The data restructuring instructions include "flip", "zip" and "unzip" instructions.