Abstract: A circuit for detecting a synchronous word signal from a moving picture experts group (MPEG) bit stream in a video-audio decoding system which is capable of more easily detecting a synchronous word by detecting a data start position of an input bit stream used for a multimedia system using the moving picture experts group (MPEG) detecting identical level bits from a bit stream inputted, and comparing the bits at a time.

Abstract: A method for processing user-input that may include a command to abort a previously requested operation and typed-ahead data entered in anticipation of completion of the previously requested operation is disclosed. The user-input is represented by a value queued in a first queue by an operating system. According to the present invention, the value is removed from the first queue and examined to determine if it represents a command to abort the previously requested operation. If the value represents a command to abort the previously requested operation, the previously requested operation is aborted. If the value does not represent a command to abort the previously requested operation, the value is queued in a second queue, and, after completion of the previously requested operation, the value is removed from the second queue and associated with a display window to which user-input is focused at that time.

Abstract: A device and method for comparing cancel tags, and for canceling data from a finite wrap-around data buffer. The data buffer stores tag values that are continuous, or sequential. A cancel tag is used to cancel all tags with a value "greater-than" the cancel tag. In comparing cancel tags of a wrap-around buffer, however, the comparator must take into account wrap-around conditions. When a wrap-around condition occurs, tags that have a lower value may be "greater-than" the cancel tag. The present invention advantageously adds an additional bit to the tags stored in the data buffer and the cancel tag. The additional bit is toggled whenever a wrap-around condition occurs. By comparing the additional bit of the tag to the additional bit of the cancel tag, a wrap-around condition can be detected without extensive additional circuitry. The comparison of the additional bit indicates whether the comparator should cancel tags that are greater-than or less-than the cancel tag.

Abstract: A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number of iterations of the loop. The microcode sequence that implements the loop includes a microcode instruction that uses the string count as an operand and/or a result. The microcode instruction unit captures the string count when it is available on either an operand or address bus. The string count is compared to the number of iterations of the string loop to determine when to terminate the microcode loop. If the string count is not captured prior to the microcode instruction unit dispatching more microcode instructions than necessary, the microcode instruction unit notifies other components via a cancel bus. In this manner, the end of a loop is detected prior to the functional unit detecting a mispredicted branch instruction within the microcode loop.

Abstract: A bit collation method is disclosed which requires a substantially fewer number of clock cycles than the prior art method in separating the bits in a source of bytes and collating them by bit position. A static look-up table is used to spread out the bits in a byte being collated. The look-up table enables simultaneous collation of all bits in a byte using only five clock cycles.

Abstract: A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.

Abstract: A first embodiment of a circuit configured to be coupled to a network controller and a network is disclosed. The first embodiment includes a first circuit configured to receive bits of data from the network at a first frequency. The first embodiment also includes a second circuit, coupled to the first circuit. The second circuit is configured to generate, to the network controller, a first signal synchronous with a second frequency when the first circuit receives a predetermined number of bits. In response to the first signal, the network controller is configured to latch, at a second frequency, the predetermined number of bits. A second embodiment of a circuit configured to be coupled to a network controller and to a network is provided. The second embodiment includes a first circuit configured to transmit bits of data (bits) to the network at a first frequency. The second embodiment includes a second circuit, coupled to the first circuit.

Abstract: A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A superscalar complex instruction set computer ("CISC") processor (100) having a reduced instruction set computer ("RISC") superscalar core (110) includes an instruction cache (104) which identifies and marks raw x86 instruction start and end points and encodes "pre-decode" information, a byte queue (106) which is a queue of aligned instruction and pre-decode information of the "predicted executed" state, and an instruction decoder (108) which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue. The instruction decoder includes in each dispatch position a logic-based conversion path, a memory-based conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer (400) directs x86 instructions from the byte queue to the conversion paths.

Abstract: The present invention which makes use of knowledge developed at the program writing stage by the programmer or by software tools such as a compiler that some substantial number of data accesses would miss in the cache hierarchy to the detriment of performance and that it would be possible to prefetch the necessary data in parallel with performing useful work. The invention provides a background memory move (BMM) mechanism by which the program can specify such prefetching of data from main memory to a quickly-accessible data cache and by which the program can determine which such prefetches have completed. This mechanism makes it possible to improve the performance of the computer system through the effective use of added concurrency while avoiding the overheads of process-swapping.

Abstract: A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).

Abstract: A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

Abstract: In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of receiving a first address of a first type and receiving a next address of the first type. Information is accumulated regarding differences between the first address and the next address. The method also includes receiving an address of a second type and using the accumulated information to determine whether the address of the second type is an address associated with a command whose execution can create a hazard. A hazard indication is generated if it is determined that the address of the second type is an address associated with a command whose execution can create a hazard. In one embodiment, the first type of address is an address associated with a first type of command and the second type of address is an address associated with a second type of command.

Abstract: Method and apparatus for determining an enforceable policy applicable to one or more network devices. The method includes attaching one or more rule elements to one or more domain elements to create policies, the domain elements representing network devices and groups of network devices, and the rule elements defining actions, a method for determining whether a conflict exists between the polices, and a method for resolving the conflicts to produce one or more enforceable policies.

Abstract: Method and apparatus for selectively controlling interrupt latency in a data processing system (10). In one embodiment, the present invention uses an interrupt control register bit field (50) to determine whether or not execution of an instruction may be interrupted by an interrupt request before execution of the instruction has completed. In some embodiments of the present invention, a first set of instruction may be interrupted mid-execution, while a second set of instructions always complete execution. Which instructions belong to the first set of instructions may be user programmable (e.g. by register bit field 52) or may be fixed. It is advantageous in some data processing systems (10) to define the instructions having the longest execution times as being part of the first set of instructions in order to reduce interrupt latency.

Abstract: A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is generated therefrom, for example, by referencing a lookup table. The microcode event handler vector is then used for invoking a microcode event handler to handle occurrence of these events in the processor. By the formation of an event vector, and the microcode event handler vector, execution performance is increased due to avoiding conditional branching within the processor, such as modem high performance architectures, including those which execute instructions in and out-of-order.

Abstract: A method for distributing broadcast data is disclosed. A first plurality of data relating to a television program is listed on a script. A second plurality of data relating to a web page is listed on the script. The script is formatted into HyperText Markup Language (HTML) format. The script is stored onto a public server.

Abstract: A superscalar microprocessor is provided having a load/store unit which receives a pair of pointers identifying the oldest outstanding instructions which are not in condition for retirement. The load/store unit compares these pointers with the reorder buffer tags of load instructions that miss the data cache and store instructions. A match must be found before the associated instruction accesses the data cache and the main memory system. The pointer-compare mechanism provides an ordering mechanism for load instructions that miss the data cache and store instructions.

Abstract: A method of controlling remote control electronic apparatus coupled to a network and a remote control electronic apparatus to be coupled to a network are disclosed. Each remote control electronic apparatus has a CPU and a ROM including a local control program expressed by an independent language which is interpretable by the CPU, a remote control program expressed by a virtual language, a virtual language processing program for processing the virtual language to make it interpretable by the CPU. When one remote control electronic apparatus is required to control another remote control electronic apparatus coupled to the network, the remote control electronic apparatus requests to transmit the remote control program of another remote control apparatus.