Abstract: A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the microprocessor. The future file is configured to store a reorder buffer tag that corresponds to the last instruction, in program order, stored within the instruction storage that has a destination operand corresponding to the register associated with said storage location. The future file is further configured to store instruction results. The control unit is configured to read a particular reorder buffer tag from the future file that corresponds to a completed instruction and to compare the particular reorder buffer tag with the completed instruction's result tag. If the two tags compare equal, the control unit is configured to write any result data corresponding to the completed instruction into the future file. This advantageously reduces the number of comparators needed to maintain the future file.

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. This capability is realized by providing a sense mechanism for detecting a no-change condition in the states associated with a controller arranged in the Arbitrated Loop.

Abstract: A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.

Abstract: An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller.

Abstract: A host node is provided with an I/O port and a display monitor. The I/O port transmits packets to a specific one of the remotely accessible server nodes containing a request for information. In response, the I/O port receives packets containing requested information, entries describing other topics of information that can be provided from the specific server node and entries describing other server nodes. The display monitor has a view area on which images are displayed. The display monitor displays a hierarchically organized table. The table includes the entries describing remotely accessible server nodes and the entries describing topics of information that can be retrieved from the remotely accessible server nodes. The entries are hierarchically organized so as to indicate a hierarchical organization of the entries as provided for retrieval from the remotely accessible server nodes which hierarchical order of retrieval is independent of a specific order of retrieval by the host node.

Abstract: A method of triggering video imaging and/or audio data on a "HyperCD" (CD-ROM) via a trigger through a network for instant local access of encrypted data on local media. The CD-ROM contains video/audio files that have been crippled by removing the critical information thereof. The CD-ROM also contains programs for directly and automatically connecting the end-user's computer to a targeted server (URL) a network (such as the Internet).

Abstract: Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that the data storage element corresponding to the full control circuit should transfer its data to the next storage element corresponding to the empty control circuit, the detection circuit generates a "move" signal. The "move" signal sets the preceding control circuit to empty and the following control circuit to full, thereby enabling movement of a data element from the preceding to the following stage. Because the control circuits are relatively simple and have predictable signal propagation times, the relative reactions of two adjacent control circuits to the common move signal can be tightly controlled. The control circuitry may control a counterflow pipeline, a forking pipeline, or a merging pipeline.

Abstract: A pipeline conveys a control word and a steering word with each instruction. The control word specifies the control signals for the instruction at each pipeline stage. The steering word specifies the routing of the instruction through the pipeline stages. Many pipeline modifications may be made by modifying the control words and steering words corresponding to the instructions. According to one embodiment, the execution pipeline within the microprocessor employs the control word/steering word method of pipeline control. Certain instructions do not perform any multiplication operations, and so may bypass the multiply pipeline stage or stages. Similarly, other instructions do not perform addition operations and may bypass the adder pipeline stage or stages. Still further, data movement and control update type instructions may bypass the pipeline all together and move directly to the result queue in the FPU.

Abstract: A facility for permitting self-deletion of application programs from a computer's mass-storage device is disclosed. The facility includes a component that tracks new files added in the course of program installation, as well as any modifications to permanent (e.g., system) files. An associated deletion component, actuable by a user, removes the added files from mass storage and reverses changes made to the permanent files. In one embodiment, the two components of the invention are associated with individual application programs; in another embodiment, the components are permanent features of the operating system or graphical user interface, and the tracking component maintains separate information for all application programs as these are installed.

Abstract: A communications system facilitates transactions between a sender and a plurality of recipients as part of an electronic messaging system. Messaging means enable a sender to form an electronic template containing a message in the form of a structured response object for a recipient as part of a transaction between a sender and a recipient(s). Controller means receive and store the message in a virtual mailbox assigned to the transaction for access by the sender and the recipient(s). The controller means generate and send to the recipients an indicator or pointer identifying the message at an address for the virtual mailbox. The recipient(s) use the pointer address to view the electronic message in the form of a structured object response at the virtual mailbox in the controller. The recipient may ignore or file the message or send a response to the virtual mailbox. The response or lack of response to the structured object response by the recipient (s) is tracked and recorded by the controller.

Abstract: A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instruction includes words which contain an operation code directing the operation of one of the functional units, a dispersal code, and a delimiter code, wherein an alignment circuit parses each compacted instruction from the buffer based upon the delimiter codes of the words and aligns the compacted instruction in an alignment buffer and a dispersal circuit transfers each word of the compacted instruction stored in the alignment buffer into at least one operational field of a dispersed instruction buffer which stores an executable instruction having an operational field corresponding to each one of the functional units.

Abstract: A microprocessor configured to detect a memory operation having a predefined data address is provided. The predefined data address indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, a second memory operation having the predefined data address indicates that instructions subsequent to the second memory operation belong to the original instruction set. The memory operations effectively provide a boundary between the instructions from dissimilar instruction sets. Instructions are routed to an execution unit configured to execute the instruction set indicated by the most recently detected memory operation having the predefined address. Each instruction sequence within the program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. The program may be executed more quickly than an equivalent program coded entirely in either instruction set.

Abstract: An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connected processor to have the connected processor resolve instructions. Each processor capable of being invoked by a connected processor to resolve instructions at the invocation of the connected processor.

Abstract: method of matching computer wild card patterns involves comparing first and second character strings associated with named objects residing on a computer system to determine whether the first character string defines a first group of computer objects which is a logical subset of a second group of computer objects defined by the second character string. The first character string is provided by a user; such as in a command line, and the second character string is pre-defined, such as by a network administrator. The method can be performed by examining whether the second character string has any wild card character which can substitute for one and only one character, or by examining whether the second character string has any wild card character which can substitute for any number of characters, including no characters (a universal character). The second character string can further be examined to see if it contains any embedded sequence of characters having no universal wild card character.

Abstract: In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2.sup.N CPUs, a method of performing a read-and-modify instruction. Data stored in a shared information register is read from the shared register, captured in a read and increment circuit and sent to the processor issuing the read-and-modify instruction. At the same time, a mathematical function is performed on the captured data is incremented and the result is written back into the shared information register.

Abstract: A method of providing a document to a client coupled to a server is provided. The server provides a number of Internet services to the client, including functioning as a caching proxy on behalf of the client for purposes of accessing the World Wide Web. The proxying server includes a persistent document database, which stores various attributes of all documents previously retrieved in response to a request from a client. When a Web document is retrieved from a remote server in response to a request from the client, the database is consulted and the stored information relating to the requested document is used by the server in transcoding the document. The document is transcoded for various purposes, including to circumvent bugs or quirks found in the document, to size the document for display on a television set, to improve transmission efficiency of the document, and to reduce latency. The transcoder makes use of the document database to perform these functions.

Abstract: The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle. In a multistage pipeline, a first stage is bypassed to provide instructions to a second stage regardless of the ability of the first stage to store the instruction from the instruction issuing unit.

Abstract: A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the microprocessor. The future file is configured to store a reorder buffer tag that corresponds to the last instruction, in program order, stored within the instruction storage that has a destination operand corresponding to the register associated with said storage location. The future file is further configured to store instruction results. The control unit is configured to read a particular reorder buffer tag from the future file that corresponds to a completed instruction and to compare the particular reorder buffer tag with the completed instruction's result tag. If the two tags compare equal, the control unit is configured to write any result data corresponding to the completed instruction into the future file. This advantageously reduces the number of comparators needed to maintain the future file.

Abstract: A microprocessor having a saturation operation unit comprising a decoder 220 for decoding a 4-bit saturation operation bit length data item into a 16-bit value, a decoder 221 for decoding a 5-bit saturation operation bit length data item into 1 to a 32-bit value, selectors 236, 237, 238, 239 and an operation unit 250 for outputting values stored in the decoder 220 and 221 or values obtained by inverting the values, per bit, stored in the decoder 220 and 221 when a target saturation operation value is over a saturated value detected by using selectors 234, 235 and operation units 226 and 227.

Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit.