Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract: A transistor array panel according to an exemplary embodiment includes a substrate, and a first transistor and a second transistor positioned on the substrate. Each of the first transistor and the second transistor includes: a first electrode; a second electrode overlapping the first electrode; a spacing member positioned between the first electrode and the second electrode; a semiconductor layer extending along a side wall of the spacing member; and a gate electrode overlapping the semiconductor layer. A thickness of the spacing member of the first transistor is larger than a thickness of the spacing member of the second transistor.

Abstract: A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of transistors. An oxide is deposited over the source and drain of the transistors. A block mask is placed over the first transistor, and the oxide is removed from the second transistor. The block mask is removed and an epitaxial growth is performed on the second transistor. A selective nitridation is performed on the second transistor, and the process is repeated for the first transistor. Other embodiments are also described.

Abstract: A method can include deriving a cloud of microseismic events corresponding to a fracturing operation in an environment by spatially locating the microseismic events in the environment via a seismic velocity model; extracting a set of fracture planes from the microseismic cloud; assigning characteristics to the fracture planes; determining a second-rank fracture compliance tensor and a fourth-rank fracture compliance tensor based on the characteristics of the fracture planes; determining a change in elastic stiffness of the environment using the second-rank fracture compliance tensor and the fourth-rank compliance tensor; and updating the seismic velocity model based at least in part on the change in the elastic stiffness of the environment or determining permeability in the environment based at least in part on fracture plane locations, orientations and apertures. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: There are disclosed a semi-transmissive, semi-reflective display panel, a method of manufacturing the same and a display device. The semi-transmissive, semi-reflective display panel includes a display substrate having a transmissive region and a reflective region, and an optical device. The optical device includes a first reflective portion and a second reflective portion; the first reflective portion is configured to reflect the light irradiating the reflective region of the display substrate from a backlight source to the second reflective portion; and the second reflective portion is configured to transmit the light irradiating the transmissive region of the display substrate from the backlight source and reflect the light reflected from the first reflective portion to the transmissive region of the display substrate.

Abstract: A package for an optical sensor, comprises an optically opaque enclosure for forming a cavity when mounted onto a substrate and an optical element based on an optically translucent polymer. An aperture in the enclosure is designed to attach the optical element to the enclosure.

Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

Abstract: Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided.

Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

Abstract: System and methods for data logging are disclosed. The method comprising performing an initialization process, performing a data collection process in which data from a plurality of sensors is collected and time stamped, performing a time correction on the time-stamp data based on patterns of time and occupancy, performing an estimation of a light state based on the corrected time stamped data and determining an energy saving using an automatic light operation based on determined light state estimation.

Abstract: A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure. The isolation structure disposed on the substrate to isolate the gate-stacked structure from the substrate has different thicknesses in different portions.

Abstract: An electroluminescent display device includes a substrate; a first electrode on the substrate; a hole auxiliary layer on the first electrode; a light emitting material layer on the hole auxiliary layer; an electron auxiliary layer on the light emitting material layer; a second electrode on the electron auxiliary layer; and insulation layers between the hole auxiliary layer and the light emitting material layer and between the electron auxiliary layer and the light emitting material layer, wherein a refractive index of the insulation layers is smaller than a refractive index of the light emitting material layer.

Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.

Abstract: A semiconductor device chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor device disposed on the first surface of the semiconductor substrate, an interconnect pattern having an end connected to the semiconductor device and another end exposed on a surface of a function layer disposed on the first surface of the semiconductor substrate, plurality of external connection electrodes mounted on the surface of the function layer and electrically connected to the other end of the interconnect pattern, an electromagnetic wave shield film for shielding electromagnetic waves, which is disposed on the second surface of the semiconductor substrate and side surfaces of the function layer, and a ground interconnect electrically connected to the electromagnetic shield film and disposed on the function layer.

Abstract: Monitoring systems and apparatuses and methods for using same are generally described. A gas monitoring system may include a base component and a module component. The module may be configured to be operably coupled to the base component through corresponding interface connectors. The system may be monitor for gases and generate alarms relating thereto, when the module is connected to the base. The base and/or module may have limited or no functionality when disconnected from the module and/or base. The module may include components that typically have an increased potential for upgrades, replacement, maintenance, or other modifications. The base may include components that typically have a lower rate of being upgraded, replaced, or requiring maintenance. In this manner, high maintenance components may be arranged in a module that has a smaller and more portable form factor as compared to the base and the system overall.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

Abstract: An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.