Abstract: A method is described for seismic imaging of the subsurface using dip-guided optimized stacking. The method computes weighting functions for a plurality of single-shot migrated images, unstacked seismic images, or partially stacked seismic images based on a slant stack performed using an input dip dataset; applying the plurality of weighting functions to the plurality of single-shot migrated images, unstacked seismic images, or partially stacked seismic images, or a plurality of dip-filtered images to create a plurality of weighted images; and summing the plurality of weighted images into a stacked seismic image. The method may be executed by a computer system.

Abstract: A display device may include an organic light emitting device and an encapsulation structure provided on the organic light emitting device to seal the organic light emitting device. The encapsulation structure may include a first inorganic encapsulation layer provided on the organic light emitting device, an organic encapsulation layer provided on the first inorganic encapsulation layer, and a second inorganic encapsulation layer provided on the organic encapsulation layer. The first inorganic encapsulation layer may include a first inorganic layer provided on the organic light emitting device and a first plasma-treated layer provided on the first inorganic layer. The first plasma-treated layer may include an upper portion, in which a rugged structure is defined.

Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.

Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Abstract: An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.

Abstract: A method for enhancing visual representation of a geologic feature in 3D seismic survey data, comprising the steps of: (a) generating a plurality of first attribute volumes, each comprising at least one characterising attribute, derivable from said 3D seismic data and different from the characterising attributes of any one of the other said plurality of first attribute volumes; (b) generating a plurality of filtered attribute volumes for each one of said plurality of first attribute volumes, utilizing a plurality of distinct filter settings at each one of said at least one characterising attribute; (c) generating a composite attribute volume by selectively combining one or more of said plurality of filtered attribute volumes so as to maximise visual detectability of said geologic feature.

Abstract: A p+-type anode region that forms a contact of an anode electrode on a front surface of a semiconductor substrate and a p+-type starting substrate of a rear surface of the semiconductor substrate is formed on the front surface of the semiconductor substrate, whereby an up-anode type vertical diode is configured. The semiconductor substrate has a p?-type epitaxial layer stacked on the p+-type starting substrate, and a p-type transition layer in a surface layer of the p?-type epitaxial layer, facing the p+-type starting substrate. A p-type anode diffusion region is provided between a p+-type surface anode region and the p-type transition layer, and contacts the p+-type surface anode region and the p-type transition layer. A p-type impurity concentration of the p-type anode diffusion region decreases from an interface with the p+-type surface anode region toward an interface with the p-type transition layer.

Abstract: A molecular detection apparatus according to an embodiment includes: a collection unit collecting detection target gas containing molecules to be detected; a detector including a plurality of detection cells each having an organic probe disposed at a sensor unit, the organic probe capturing the molecules collected in the collection unit; and a discriminator discriminating the molecules by a signal pattern based on an intensity difference of detection signals generated by the molecules being captured by the organic probes in a plurality of the detection cells. In the molecular detection apparatus according to the embodiment, at least one of the detection cells has a plurality of different types of the organic probes disposed at the sensor unit.

Abstract: An optoelectronic semiconductor chip (10) is specified, comprising a p-type semiconductor region (4), an n-type semiconductor region (6), and an active layer arranged between the p-type semiconductor region (4) and the n-type semiconductor region (6), said active layer being designed as a multiple quantum well structure (5), wherein the multiple quantum well structure (5) comprises quantum well layers (53) and barrier layers (51), wherein the barrier layers (51) are doped, and wherein undoped intermediate layers (52, 54) are arranged between the quantum well layers (53) and the barrier layers (51). Furthermore, a method for producing the optoelectronic semiconductor chip (10) is specified.

Abstract: According to one embodiment, a semiconductor includes a first wiring, a second wiring, a first electrode, a second electrode and a memory cell. The first wiring extends in a first direction. The second wiring extends in a second direction crossing the first direction. The first electrode is connected to the first wiring. The second electrode is connected to the second wiring. The memory cell is arranged between the first electrode and the second electrode. The memory cell includes a memory element electrically connected to the first electrode, and a selector provided between the memory element and the second electrode and electrically connected to the second electrode, and the memory element and the selector are of a same conductivity type.

Abstract: A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.

Abstract: A metal-insulator-metal (MIM) capacitor includes a semiconductor substrate and a capacitor device. The capacitor device includes a first conductor upright on the semiconductor substrate, a second conductor upright on the semiconductor substrate, and an insulator disposed used for insulating the first conductor from the second conductor. In a method for fabricating the capacitor device, a mask including a test line pattern and a capacitor pattern with a first trench pattern and a second trench pattern is used to form a test line and the first conductor and the second conductor of the capacitor device, thereby decreasing the cost of for fabricating the MIM capacitor.

Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.

Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Abstract: A memory device includes: a first conductive column structure extending through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure; and a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of the other end of the shell portion of the first conductive column structure.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.

Abstract: A time-of-flight (TOF) sensor includes a light source, a plurality of avalanche photodiodes, and a plurality of pulse generators. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, and the control circuitry includes logic that when executed by the control circuitry causes the time-of-flight sensor to perform operations. The operations include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. A plurality of pulses is output from the individual pulse generators corresponding to the individual avalanche photodiodes that received the light, and a timing signal is output when the plurality of pulses overlap temporally. A time is calculated when a first avalanche photodiode in the plurality of avalanche photodiodes received the light.