Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract: The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.

Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.

Abstract: The invention relates to a component (10) having a semiconductor layer sequence, which has a p-conducting semiconductor layer (1), an n-conducting semiconductor layer (2), and an active zone (3) arranged between the p-conducting semiconductor layer and the n-conducting semiconductor layer, wherein the active zone has a multiple quantum well structure, which, from the p-conducting semiconductor layer to the n-conducting semiconductor layer, has a plurality of p-side barrier layers (32p) having intermediate quantum well layers (31) and a plurality of n-side barrier layers (32n) having intermediate quantum layers (31). Recesses (4) having flanks are formed in the semiconductor layer sequence on the part of the p-conducting semiconductor layer, wherein the quantum well layers and/or the n- and p-side barrier layers extend in a manner conforming to the flanks of the recesses at least in regions. The interior barrier layers have a larger average layer thickness than the p-side barrier layers.

Abstract: A present invention includes a negative electrode, a substrate, an adhesive layer, an insulation layer and a reflective layer sequentially stacked. A P-type semiconductor layer, a light emitting layer and an N-type semiconductor layer are sequentially stacked on the reflective layer to form an LED light emitting layer. A positive electrode, spaced from the LED light emitting layer, is further stacked on the reflective layer. The present invention further includes an electrical connection structure that penetrates through the insulation layer, and penetrates through, in a spaced manner from the insulation layer, the reflective layer, the P-type semiconductor layer and the light emitting layer. The electrical connection structure is electrically connected to the adhesive layer and the N-type semiconductor layer, and has a pattern distribution. The pattern distribution is least one strip-like shape to form the continuous electrode structure.

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i?2.