Abstract: An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

Abstract: An electronic system includes a plurality of heat sources. At least two of the plurality of heat sources vary in height and each of the plurality of heat sources includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each of the plurality of heat sources is positioned adjacent to the first side of the substrate. The electronic system further includes a cover member provided above the plurality of heat sources and a sintering thermal interface material provided between the cover member and the first side of one of the at least two heat sources that vary in height.

Abstract: Disclosed is a semiconductor device package comprising: first insulation layers disposed between first wiring lines and second wiring lines; a plurality of first pads electrically connected to the first wiring lines, respectively; and a plurality of second pads electrically connected to the second wiring lines, respectively, wherein the line having the longest length extended in a first direction, among the plurality of first wiring lines, has an area of a region, which is overlapped with an electrically connected semiconductor structure, that is larger than that of the line having the shortest extended length.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: A method of manufacturing a light source device includes: disposing bumps containing a first metal on a first substrate which is thermally conductive; disposing a bonding member on the bumps, the bonding member containing Au—Sn alloy; disposing a light emitting element on the bumps and the bonding member; and heating the first substrate equipped with the bumps, the bonding member, and the light emitting element.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.

Abstract: A method for producing an electronic arrangement includes providing an aluminium body and a power electronic unit. The power electronic unit includes a base plate and an electronic component. The method includes pre-treating a joining region of a main surface of the aluminium body; coating the pre-treated joining region with a sinter paste including at least one of copper particles and silver particles; positioning the power electronic unit with a second side of the base plate on the main surface of the aluminium body; joining the power electronic unit and the aluminium body in the joining region with supply of heat, wherein the aluminium body and the power electronic unit are connected via the sinter paste in a materially bonded and heat-transferring manner.

Abstract: Provided is a highly reliable semiconductor device capable of reducing stress generated in a semiconductor element even when a highly elastic joining material such as a Pb-free material is used in a power semiconductor having a double-sided mounting structure. The semiconductor device includes a semiconductor element including a gate electrode only on one surface, an upper electrode connected to the surface of the semiconductor element on which the gate electrode is provided, and a lower electrode connected to a surface opposite to the surface of the semiconductor element on which the gate electrode is provided.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect.

Abstract: A transfer device for a micro light-emitting diode (micro LED) of the present application includes a collecting tube and a driving device. The collecting tube has a first end and a second end disposed oppositely, and the collecting tube includes a collecting opening and a storage tube, and the collecting opening is connected to the storage tube, and the collecting opening is disposed at the first end. The driving device is disposed at the second end, and the driving device is configured to provide a driving force, wherein the driving device is configured to provide the driving force to pick up the micro LED from the collecting opening into the storage tube so that the storage tube is able to store and stack at least two micro LEDs.

Abstract: A method of manufacturing a flexible display includes providing a substrate having a first and second pad density areas and a pair of long sides; forming conductive pads on the substrate, each of the conductive pad is free of right angle and in a shape of parallelogram, and a pad density of the second pad density area is higher than that of the first pad density area; providing a flexible substrate; and bonding the conductive pads to a conductor of a circuit of the flexible substrate. Each of the conductive pad has long sides and short sides, a portion of the conductive pads have the long sides sloped away from the first pad density area and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped away the first pad density area and toward the other long side of the substrate.

Abstract: An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

Abstract: A semiconductor apparatus includes: an insulating substrate including a circuit pattern; a semiconductor device mounted on the insulating substrate and electrically connected to the circuit pattern; a case storing the insulating substrate and the semiconductor device; and an electrode attached to the case, wherein a tip surface of the electrode is jointed to the circuit pattern with solder, the electrode is brought into contact with and pushed against the circuit pattern by the case, and a projection is provided on the tip surface.

Abstract: A wavelength conversion device that includes a plurality of crystal layers adjacent to one another such that crystal-axis orientations thereof are alternately arranged, the plurality of crystal layers each including a first-thickness portion having a first thickness and a second-thickness portion having a second thickness smaller than the first thickness; and an adhesive layer in at least part of a gap between adjacent second-thickness portions of the plurality of crystal layers and with which the plurality of crystal layers are bonded to one another.