Abstract: In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.

Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.

Abstract: A switching method, including: electrically coupling a switching circuit to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generation circuit and a negative terminal of the frequency generation circuit; adjusting an impedance value of the second impedance circuit according to a first clock signal and a second clock signal outputted by the frequency generation circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit by a first switching unit of the switching circuit; and periodically conducting the positive terminal to the other one of the first impedance circuit and the second impedance circuit by a second switching unit of the switching circuit.

Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: A filter includes a multilayer substrate and resonators (8), (11), and (14) at three stages provided in the multilayer substrate and coupled to a next stage. The multilayer substrate is provided with a floating electrode for coupling an open end portion (9A2) of a linear conductor of the resonator (8) at an input stage and an open end portion (12B2) of a linear conductor of the resonator (11) at an output stage. The multilayer substrate is provided with a floating electrode for coupling an open end portion (9B2) of the linear conductor of the resonator (8) at the input stage and an open end portion (12A2) of the linear conductor of the resonator (11) at the output stage.

Abstract: Disclosed herein is a waveguide for use in a linear accelerator. The waveguide comprises cells arranged to receive a beam of charged particles therethrough along a particle path, and is configured to receive an electromagnetic field from a source of electromagnetic radiation. A plurality of the cells are individually switchable cells, with each individually switchable cell comprising a respective switch configured to adjust the supply of electromagnetic radiation to the individually switchable cell.

Abstract: A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.

Abstract: In some examples, a circuit includes an amplifier, a resistor, and a damping network. The amplifier has an amplifier output and first and second amplifier inputs. The first amplifier input is adapted to be coupled to a first terminal, and the second amplifier input is configured to receive a reference voltage. The resistor is coupled between the amplifier output and the first amplifier input. The damping network is coupled between the amplifier output and the first terminal.

Abstract: Frequency multipliers (300) for generating a differential output signal from a single-ended input signal are disclosed. The frequency multiplier comprises a single-ended input (Pin(f0)) to receive the input signal with a frequency of f0 and differential outputs (+/?Pout(2nf0)) to provide the differential output signals. The frequency multiplier further comprises a first signal branch (301) connected to the single-ended input and one of the differential outputs (+Pout(2nf0)). The first signal branch comprises a first low pass or bandpass filter with a center frequency of f0 (L/BPF1), a first nonlinear component (NC1) and a first high pass or bandpass filter with a center frequency of 2nf0 (H/BPF1). The frequency multiplier further comprises a second signal branch connected to the single-end input and another one of the differential outputs (?Pout(2nf0)).

Abstract: A radio frequency integrated circuit (RFIC) and method of communication are provided. The RFIC includes phased-locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes comprising at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers.

Abstract: Apparatus and methods for signal conditioning of radio frequency signals are provided. In certain embodiments, a mobile device includes a transceiver configured to output a differential transmit signal and to receive a single-ended receive signal, and a front end system. The front end system includes a transmit balun, a differential transmit amplifier configured to amplify the differential transmit signal to generate an amplified differential transmit signal provided to a first winding of the transmit balun, a differential receive amplifier configured to amplify a differential receive signal received from the first winding to generate an amplified differential receive signal, and a receive balun configured to convert the amplified differential receive signal into the single-ended receive signal.

Abstract: A self-diagnostic system and method is provided for a transceiver. The self-diagnostic system and method includes a controller and switching circuitry. The switching circuitry is connected to the transceiver and has two positions. The first position of the switching circuitry connects the transmitter and receiver of the transceiver to an antenna system and the second position of the switching circuitry connects the transmitter to the receiver via a power attenuator. After switching the switching circuitry to the second position, the controller initiates the diagnostic procedure by sending a signal to the transceiver. Upon receipt of the signal from the controller, the transceiver initiates the diagnostic procedure by having the transmitter send a preselected output signal to the receiver via the switching circuitry. During the diagnostic procedure, parameters of interest are measured and reported to the controller.

Abstract: A device and method for correcting in-phase and quadrature phase (IQ) baseband components to drive a speaker is provided. The device: controls a local oscillator of an RF downmixing device to a plurality of baseband frequency offsets over a range that includes a given baseband frequency offset; determines, at the plurality of baseband frequency offsets, for a received RF signal, amplitude ratio error and phase error for respective IQ baseband components of the received RF signal; generates, using the amplitude ratio error and the phase error for the respective IQ baseband components, for the given offset, filter coefficients for a given baseband frequency range which compensates for respective amplitude ratio error and respective phase error for the given baseband frequency range; and filters, with the filter coefficients, IQ baseband components of the received RF signal, with the local oscillator operating at the given offset, to generate corrected IQ baseband components.

Abstract: A geolocationing system and method for providing awareness in a multi-space environment, such as a hospitality environment or educational environment, are presented. In one embodiment of the geolocationing system, a vertical and horizontal array of gateway devices is provided. Each gateway device includes a gateway device identification providing an accurately-known fixed location within the multi-space environment. Each gateway device includes a wireless transceiver that receives a beacon signal from a proximate wireless-enabled personal locator device. The gateway devices, in turn, send gateway signals to a server, which determines estimated location of the wireless-enabled personal locator device with time of arrival modeling.

Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.

Abstract: A gate drive device for driving a switching element includes: a gate drive circuit that drives a gate of the switching element based on a gate drive signal and a drive performance adjustment signal; a gate voltage detection circuit that outputs an on detection signal or an off detection signal when detecting that a gate voltage of the switching element reaches an on determination set value or an off determination set value; and a control circuit that outputs the drive performance adjustment signal to the gate drive circuit to match a gate drive time with a predetermined gate drive time set value.

Abstract: A differential tuned inductor and a multilayer tunable transformer for an integrated circuit device for microwave and RF applications are disclosed. The tunable inductor can be used in differential artificial delay lines to achieve delay tuning while preserving impedance matching. The tunable transformer can also be used for mixer drives to achieve wider operational performance.

Abstract: Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.