Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.

Abstract: The disclosure features wireless energy transfer sources that include at least two source resonators and a power source, where: each of the at least two source resonators has a nominal impedance when a device resonator is not positioned on or near any of the at least two source resonators, the nominal impedances of each of the at least two source resonators varying by 10% or less from one another; and the at least two source resonators are configured so that during operation of the wireless energy transfer source, when a device resonator is positioned on or near a first one of the at least two source resonators: (a) the impedance of the first source resonator is reduced to a value smaller than the nominal impedances of each of the other resonators by a factor of 2 or more.

Abstract: Methods and apparatus for reducing electromagnetic interference (EMI) in power conversion stage line filter are provided herein. The method, for example, includes determining an estimated ripple voltage or estimated ripple current using a predictive model, generating a ripple cancellation signal of opposite polarity to the estimated ripple voltage or ripple current, while compensating for at least one of magnitude or phase distortions in a signal path, and injecting the ripple cancellation signal into a power supply's line filter to reduce a ripple voltage.

Abstract: Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

Abstract: In some examples, a circuit includes an amplifier, a resistor, and a damping network. The amplifier has an amplifier output and first and second amplifier inputs. The first amplifier input is adapted to be coupled to a first terminal, and the second amplifier input is configured to receive a reference voltage. The resistor is coupled between the amplifier output and the first amplifier input. The damping network is coupled between the amplifier output and the first terminal.

Abstract: A switched mode power supply comprises a communication interface including an address terminal configured to couple to an external resistor for setting a communication address of the switched mode power supply. A control circuit is configured to determine the value of the external resistor a first time with a first technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the first technique if the value of the external resistor is greater than the threshold value. The control circuit is also configured to, if the value of the external resistor is less than the threshold value, determine the value of the external resistor a second time with a second technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the second technique.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

Abstract: In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.

Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.

Abstract: A high-frequency switch circuit includes a first switch configured to electrify or cut off connection between an antenna terminal and an input terminal, and a second switch configured to electrify or cut off connection between the antenna terminal and an output terminal. The first switch has a transmission line connecting the antenna terminal and the input terminal; a diode having an anode connected to a first node between the transmission line and the input terminal, and a cathode connected to a second node; and a capacitor connected to the second node and a first power supply voltage. A first control terminal is connected to the first node via a first resistor and a first inductor. The first switch further includes a charging/discharging circuit connected to a second power supply voltage and the first control terminal and charging and discharging the capacitor from the second node.

Abstract: Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider.

Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.

Abstract: According to one embodiment, a sensor device includes a switch, a control circuit and an A/D converter. The switch is connected to a sensor element configured to store charge and provided to read the charge stored in the sensor element from the sensor element. The control circuit is configured to control the switch so as to partially and sequentially read the charge stored in the sensor element. The A/D converter is connected to the switch, which is configured to output a digital signal obtained by A/D-converting an analog signal according to the charge, for each charge partially read via the switch.

Abstract: Some aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an integrator coupled between a first node and a second node and a filter coupled between the second node and a third node. The circuit further includes a buffer coupled between the third node and a fourth node and a first switch coupled between the fourth node and a fifth node. The circuit further includes a first capacitor coupled between the fifth node and a ground node, a first resistor comprising a first terminal coupled to the fifth node and a second terminal, a second switch coupled between the second terminal of the first resistor and the ground node.

Abstract: An AC inverter in a vehicle operates using a 24 V input when a vehicle powertrain is in a parked/idling state. A first 12 V battery is connected with a first bus segment. A second 12 V battery is connected with a second bus segment. A switch module selectably interconnects the first and second bus segments. In a nominal 12 V state, the batteries are connected in parallel from the bus segments to ground. In a dual voltage state, the batteries are connected in series so the first bus segment is at 12 V and the second bus segment is at 24 V. A first alternator driven by the powertrain provides a regulated voltage to the second bus segment, wherein the regulated voltage corresponds to 12 V when the switch module is in the nominal state and corresponds to 24 V when the switch module is in the dual voltage state.

Abstract: The present invention is a computationally-efficient compensator for removing nonlinear distortion. The compensator operates in a digital post-compensation configuration for linearization of devices or systems such as analog-to-digital converters and RF receiver electronics. The compensator also operates in a digital pre-compensation configuration for linearization of devices or systems such as digital-to-analog converters, RF power amplifiers, and RF transmitter electronics. The adaptive Volterra compensator effectively removes nonlinear distortion in these systems by implementing an adaptive background algorithm to periodically update actual filter coefficients to maintain optimal performance in operating conditions varying over time (e.g., temperature, frequency, signal level, and drift); or both. The xadaptive background algorithm calculates the optimal nonlinear filter coefficients to reduce nonlinear distortion.