Patents Examined by Patrick C Chen
  • Patent number: 10382013
    Abstract: Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Altera Corporation
    Inventors: Lai Guan Tang, Kris Dehnel, Benoit Herve
  • Patent number: 10359451
    Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Yu-Ri Lim, Jong-Man Im
  • Patent number: 10355685
    Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 16, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Masahisa Iida, Masahiro Gion
  • Patent number: 10355688
    Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 16, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Cameron Brown, Yashodhan Vijay Moghe
  • Patent number: 10355679
    Abstract: A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 16, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chien-Chuan Huang, Chia-Hsin Tung, Chun-Hung Chen, Hao-Jan Yang, Chieh-Hsiang Chang
  • Patent number: 10355699
    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Menno Spijker
  • Patent number: 10355671
    Abstract: Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a first passgate, a first latch, a second passgate, and a second latch. The first latch may include a first inverter and a first logic gate. The first logic gate may further include a second inverter and at least one voltage reducing component. The voltage reducing component may be an N-channel transistor or a P-channel transistor. Similarly, the second latch may include a third inverter and a second logic gate. The second logic gate may further include a fourth inverter and at least one voltage reducing component.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 16, 2019
    Assignee: LITTLE DRAGON IP HOLDING LLC
    Inventor: Mingming Mao
  • Patent number: 10340890
    Abstract: A high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 2, 2019
    Assignees: NUVOTON TECHNOLOGY CORP., NCKU RESEARCH & DEVELOPMENT FOUNDATION
    Inventors: Shuenn-Yuh Lee, Sz-An Chen
  • Patent number: 10340732
    Abstract: According to one aspect, embodiments herein provide a UPS system comprising: a plurality of UPS's configured to be coupled in parallel, each UPS comprising: a bypass line selectively coupled between an input and an output via a bypass switch, wherein the bypass switch is configured to close in a first mode and to open in a second mode, and a controller coupled to the plurality of UPS's and configured to, in response to a determination that input power is at a desired level, control the bypass switch of a first UPS in the plurality of UPS's to operate in the first mode and provide a continuous output current waveform with an RMS value to the load, and selectively control the bypass switch of each other UPS to operate in the first mode such that an output current waveform provided by each UPS includes at least one delay period.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 2, 2019
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventor: Lars Nørup Bach
  • Patent number: 10320376
    Abstract: A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Richard Geiss
  • Patent number: 10313138
    Abstract: The invention relates to a powered device (2) like a luminaire for being used in a power distribution system (100), which is preferentially a PoE system and which comprises a power sourcing device (1) for sourcing a power to the powered device. The powered device comprises an electrical load like an LED and an electrical load power providing unit for generating from the sourced power an electrical load power and for providing the electrical load power to the electrical load, wherein the electrical load power providing unit is adapted to generate the electrical load power with a power level such that an input current drawn by the powered device from the power sourcing device is maximized below a predefined upper input current threshold. This allows increasing the power consumption of the powered device in comparison to the power consumption of powered devices in accordance with the PoE standard IEEE 802.3at.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: June 4, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Lennart Yseboodt, Matthias Wendt
  • Patent number: 10296024
    Abstract: A semiconductor switch control device includes a first FET and a second FET arranged adjacent to each other, in which source terminals are connected in series. A drain terminal of the first FET is connected to a high voltage battery, and a drain terminal of the second FET is connected to a high voltage load. A controller determines a temperature state of a minus-side main relay including the second FET based on a forward voltage of a body diode of the first FET.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: YAZAKI CORPORATION
    Inventors: Mitsuaki Morimoto, Eiichiro Oishi
  • Patent number: 10291179
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10277230
    Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 30, 2019
    Assignee: Apple Inc.
    Inventors: Wenbo Liu, Ming-Shuan Chen, Sanjeev K. Maheshwari
  • Patent number: 10276681
    Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen
  • Patent number: 10270431
    Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tyler J. Gomm, Yasuo Satoh
  • Patent number: 10267655
    Abstract: A CV conversion amplifier is provided that can secure a sufficient capacitance-to-voltage conversion gain and a sufficient amplitude range of an output voltage with a small consumption current. A capacitive sensor using the CV conversion amplifier is provided with low electric power, low noise, and a wide tolerance of input signals. The CV conversion amplifier accepts outputs, as inputs, from a first capacitance and a second capacitance whose capacitance is changed depending on a physical quantity and converts a capacitance value into a voltage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Oshima, Makoto Takahashi, Yuki Furubayashi
  • Patent number: 10268228
    Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 23, 2019
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 10263608
    Abstract: A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: April 16, 2019
    Assignee: NXP USA, Inc.
    Inventors: Thierry Dominique Yves Cassagnes, Joel Cameron Beckwith, Jerome Romain Enjalbert, Dejan Mijuskovic
  • Patent number: 10250122
    Abstract: A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: April 2, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gang Chen, Gabor Reizik