Patents Examined by Patrick C Chen
  • Patent number: 11296683
    Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 5, 2022
    Assignee: SiFive, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 11290115
    Abstract: Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 29, 2022
    Assignee: KANDOU LABS, S.A.
    Inventor: Kiarash Gharibdoust
  • Patent number: 11290087
    Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 29, 2022
    Assignee: pSemi Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 11283439
    Abstract: A semiconductor device includes a power semiconductor chip, a threshold setting unit and a breaker circuit. The power semiconductor chip is connected between an output terminal and an earth terminal, and is configured to be turned on or off according to a potential at a gate terminal thereof. The threshold setting unit outputs an interrupt signal upon detecting that a voltage of a control signal received at an input terminal is lower than a predetermined voltage. The breaker circuit is connected between the gate terminal and the earth terminal, and switches on upon receiving the interrupt signal to thereby turn off the power semiconductor chip. The threshold setting unit includes a feed circuit that is configured to supply an electric charge stored in gate capacitance of the power semiconductor chip to the threshold setting unit responsive to a sudden drop of the voltage of the control signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigemi Miyazawa
  • Patent number: 11283440
    Abstract: A circuit arrangement has an even number of semiconductor switches, which are connected in series and contain in each case two load terminals and a control terminal and are associated with one another in pairs. The circuit arrangement also contains, for each semiconductor switch, a driver for actuating the semiconductor switch via the control terminal thereof and, for every two semiconductor switches that form a switch pair, contains a switching power supply which is supplied with energy from an electrical voltage between the two load terminals of a first semiconductor switch of the switch pair and supplies both the driver of the first semiconductor switch and the driver of the second semiconductor switch of the switch pair with energy.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 22, 2022
    Assignee: Siemens Energy Global GmbH & Co. KG
    Inventors: David Doering, Gerald Franz Giering, Klaus Wuerflinger
  • Patent number: 11271664
    Abstract: Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 8, 2022
    Assignee: XILINX, INC.
    Inventors: Frantz Stephane Florent Ngankem Ngankem, Kevin Geary
  • Patent number: 11271547
    Abstract: A gate drive circuit includes: a drive unit configured to drive a gate of a main circuit element including a majority carrier device; and a drive capability change unit configured to cause the drive unit to increase a drive capability of turning on the main circuit element as a main circuit current that flows through the main circuit element decreases.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: March 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hong-Fei Lu
  • Patent number: 11270031
    Abstract: The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 8, 2022
    Assignee: Drexel University
    Inventors: Ioannis Savidis, Vaibhav Venugopal Rao, Kyle Joseph Juretus
  • Patent number: 11258441
    Abstract: A drive circuit includes: a current capability switch configured to switch a current capability of driving an output transistor of a switching power supply according to whether a switch current flowing through the output transistor is in a continuous mode or in a discontinuous mode.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Shinji Takizawa, Satoru Nate
  • Patent number: 11258358
    Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 22, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Shivam Kalla
  • Patent number: 11245393
    Abstract: A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Sho Tanaka, Shigeru Kusunoki
  • Patent number: 11243599
    Abstract: A semiconductor device connectable between a first power-supply line connected to a power source and through which power is continuously supplied to a first circuit, and a second power-supply line that is not directly connected to the power source and is connected to a second circuit, includes a first switch connectable between the first and second power-supply lines and turned on in response to a signal for supplying power to the second circuit, a second switch connectable between the first and second power-supply lines and having a current supply capability higher than the first switch, and a control circuit configured to turn on the second switch when the first switch is turned on and a voltage applied to the second power-supply line has reached a threshold.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Osamu Wada
  • Patent number: 11223503
    Abstract: A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 11, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11206026
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Patent number: 11201627
    Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 14, 2021
    Assignee: Massachusetts Institute of Technology
    Inventor: Robert J. Murphy
  • Patent number: 11201619
    Abstract: The present application relates to an isolated drive circuit, of the type commonly employed as high side drivers, for providing a drive signal to a semiconductor switch. The isolated drive circuit comprises a transformer with primary and secondary windings. The circuit further comprises a primary side circuit having a plurality of switches arranged in a bridge configuration with the primary winding positioned across the output of the bridge and a secondary side circuit connected to the secondary winding of the transformer and having a drive circuit output for providing a drive signal to the semiconductor switch. The advantage of this approach is that the entire circuit can be constructed as a module for use as a single component on a circuit board without requiring additional external components.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 14, 2021
    Assignee: Heyday Integrated Circuits SAS
    Inventors: Karl Rinne, Joseph Duigan
  • Patent number: 11196159
    Abstract: A radio-frequency switch is disclosed, comprising a set of field-effect transistors disposed between a first node and a second node. In some embodiments, each field-effect transistor of the set of field-effect transistors has a respective source, drain, gate, and body. In some embodiments, the radio-frequency switch includes a compensation circuit coupled in parallel with the set of field-effect transistors, the compensation circuit configured to compensate a non-linearity effect generated by the set of field-effect transistors.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 7, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Zhiyang Liu, Nuttapong Srirattana
  • Patent number: 11190179
    Abstract: A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 30, 2021
    Assignee: Turntide Technologies Inc.
    Inventors: Alejandro Pozo Arribas, Mahesh Krishnamurthy
  • Patent number: 11175713
    Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Zeljko Zupanc, Andrew Morning-Smith, Mary Goodman, Alice Allen, Simon Ramage, Justin Elkow
  • Patent number: 11167953
    Abstract: A power supply circuit of a passenger conveyor converts includes an electrolytic capacitor and a control power supply device configured to supply an electric power to a charging circuit configured to charge the electrolytic capacitor. A storage battery is disposed between a converter and an inverter in parallel with the electrolytic capacitor. When an operation of the passenger conveyor is stopped in response to a key operation, the power supply to the control power supply device is shut off. When the operation of the passenger conveyor is resumed in response to a key operation, a DC electric power charged in the storage battery is supplied to the inverter, to thereby allow the passenger conveyor to resume the operation.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Atsushi Morigami