Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.

Abstract: A CV conversion amplifier is provided that can secure a sufficient capacitance-to-voltage conversion gain and a sufficient amplitude range of an output voltage with a small consumption current. A capacitive sensor using the CV conversion amplifier is provided with low electric power, low noise, and a wide tolerance of input signals. The CV conversion amplifier accepts outputs, as inputs, from a first capacitance and a second capacitance whose capacitance is changed depending on a physical quantity and converts a capacitance value into a voltage.

Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.

Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.

Abstract: A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.

Abstract: A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode.

Abstract: A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.

Abstract: A method for voltage balancing series-connected power switching devices (IGBTs) each connected in parallel with a respective diverter having controllable impedance to controllably conduct current diverted from the associated power switching device, the method comprising the step of controlling each diverter to follow a series of at least two successively higher impedance states during an OFF period of the power switching devices. The series of impedance states for each diverter comprises a first impedance and then a second, higher impedance, the first impedance occurring in response to an indication of a start of the OFF period. The first impedance state preferably occurs during a tail current of the power switching device in parallel with the respective diverter and the second or later impedance state during a leakage current of that power switching device.

Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.

Abstract: A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract: A frequency divider and a control method thereof are provided. The frequency divider includes a phase selector and a control circuit. The phase selector receives N input signals, and selects a first input signal from the N input signals as an output signal according to N selection signals. The frequency of the N input signals are the same, and the phase of the N input signals are different, and every adjacent two of the N input signals have a phase difference of 360°/N, wherein N is a positive integer larger than 2. The control circuit updates the N selection signals according to the output signal, such that the phase selector switches the output signal from the first input signal to a second input signal of the N input signals, wherein the phase of the second input signal leads the phase of the first input signal by 360°/N.

Abstract: According to one aspect, embodiments of the invention provide a UPS comprising a delta transformer having a primary winding and a secondary winding, the primary winding coupled between an input and an output and the secondary winding having a first end and a second end, a delta inverter coupled between a DC bus and the secondary winding, a short circuit control circuit selectively coupled between the first end and the second end of the secondary winding, a main inverter coupled between the DC bus and the output, and a controller configured to control, in a bypass mode of operation, the short circuit control circuit to couple the first end of the secondary winding to the second end such that the secondary winding is short circuited and unconditioned output AC power, derived from the input AC power via the primary winding, is provided to the output.

Abstract: An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.

Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

Abstract: A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.

Abstract: Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.