Abstract: A quantum computer comprises an apparatus having atomic objects therein; a first manipulation source configured to provide a first manipulation signal; a second manipulation source configured to provide a second manipulation signal; and a controller. The controller is configured to cause the first manipulation source to provide the first manipulation signal to a region of the apparatus; and cause the second manipulation source to provide the second manipulation signal to the region. The first manipulation signal is tuned to excite atomic objects within the region from a leaked state outside of the qubit space to an intermediary manifold and to suppress excitation of atomic objects that are in the qubit space. The second manipulation signal is tuned to excite atomic objects from the intermediary manifold to a decay manifold from which there is a non-zero probability that an atomic object will decay into the qubit space.

Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Abstract: A switched mode power supply includes a communication interface and an address terminal for setting a communication address for the power supply using the resistance of an external resistor when the external resistor is coupled to the address terminal. The power supply is configured to determine a first resistance value for the external resistor using a first technique, determine a second resistance value for the external resistor using a second technique, set the communication address of the power supply using the first resistance value if the first resistance value is greater than a threshold value, and set the communication address of the power supply using the second resistance value if the first resistance value is less than the threshold value. Other example switched mode power supplies, power systems including one or more power supplies, and methods for setting a communication address of a power supply are also disclosed.

Abstract: In the power transmission unit, a first coil pattern includes first inner side patterns, and first outer side patterns provided on the outer side of the first inner side patterns. A second coil pattern includes second inner side patterns, and second outer side patterns provided on the outer side of the second inner side patterns. The first and second coil patterns are configured such that the first inner side patterns and the second outer side pattern are connected, and the first outer side patterns and the second inner side patterns are connected. Then, the first and second coil patterns transfer power to the power transmission coil pattern of a power receiving unit in a contactless manner.

Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.

Abstract: The disclosure features wireless energy transfer sources that include at least two source resonators and a power source, where: each of the at least two source resonators has a nominal impedance when a device resonator is not positioned on or near any of the at least two source resonators, the nominal impedances of each of the at least two source resonators varying by 10% or less from one another; and the at least two source resonators are configured so that during operation of the wireless energy transfer source, when a device resonator is positioned on or near a first one of the at least two source resonators: (a) the impedance of the first source resonator is reduced to a value smaller than the nominal impedances of each of the other resonators by a factor of 2 or more.

Abstract: A device for phase adjustment preset for an N-path filter comprising a logic block; a ring divider array creating a local oscillator drive for a mixer; the ring divider array comprising: a plurality of registers, each comprising: inputs S, R, D, and clock, and output Q; the plurality of registers comprising at least: a first register; a second register; and an Nth register; a preset control word; wherein the preset control word is applied to the logic block, the logic block providing input to each of the S and the R inputs of each the register; whereby a desired starting phase of the divider is controlled. A method includes defining a desired starting conditions; determining a control word from desired starting conditions; applying control word to logic block; applying a reset signal to logic block; and outputting values for each of S and R to each register.

Abstract: An electronic circuit includes a first input pin configured to receive a first input signal that includes an enable information and at least one operation parameter information, a second input pin configured to receive a second input signal, an output pin, a control circuit configured to generate a drive signal based on the first input signal and the second input signal, an output circuit configured to generate an output signal at the output pin, the enable information includes an enabled state and a disabled state, the control circuit is configured to generate the drive signal in the enabled state and to turn to the electronic circuit off in the disabled state, the at least one operation parameter information includes information about an operational parameter of the output signal, and the output circuit is configured to use the at least one operation parameter information to change the operational parameter of the output signal.

Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

Abstract: In certain embodiments, driver circuitry generates drive signals to drive driven circuitry to transition between first and second states. The driver circuitry has a first-to-second driver circuit that generates a first drive signal to drive the driven circuitry to transition from the first state to the second state and a second-to-first driver circuit that generates a second drive signal to drive the driven circuitry to transition from the second state to the first state. The driver circuitry includes two complementary triggered current pulse generators (described in U.S. Pat. No. 10,554,206) that combine to efficiently provide switch drive for a FET or other reactive load. The triggered drive has fast edges for low switching losses. In certain embodiments, the low power triggered drive circuitry can respond to a slowly changing feedback signal to switch a FET so as to regulate a power converter output.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: A power management system for dispensers is described. The system includes a controller connected to a lower power zero net voltage (ZNV) power source. A power rectification circuit (PRC) converts ZNV power to higher voltage direct current (HVDC) power. An energy storage system connected to the HVDC power source receives and stores HVDC power within the energy storage system which is selectively provided to a dispenser motor load connected to the energy storage system. The system provides an effective solution to the problem of transferring power from a low power battery source on a disposable product to a dispenser as well as providing a system that minimizes corrosion at the electrical interface between the disposable product and the dispenser particularly in higher humidity environments.

Abstract: The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.

Abstract: A drive circuit includes: a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and a capacitor having one end connected to a high side main terminal of the switching device, wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.