Patents Examined by Patrick C Chen
  • Patent number: 10418996
    Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Molka Ben Romdhane, Berndt Gammel
  • Patent number: 10411685
    Abstract: A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 10, 2019
    Assignee: Joulwatt Technology (Hangzhou) Co., LTD
    Inventors: Pitleong Wong, Yang Lu, Yue Ji, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10411675
    Abstract: In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 10, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Jaewook Kim, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong
  • Patent number: 10390075
    Abstract: A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Munehiro Kozuma
  • Patent number: 10389238
    Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 10382014
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 13, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Ljubisa Bajic, Stephen V. Kosonocky, Steven J. Kommrusch
  • Patent number: 10382013
    Abstract: Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Altera Corporation
    Inventors: Lai Guan Tang, Kris Dehnel, Benoit Herve
  • Patent number: 10381051
    Abstract: A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP USA, INC.
    Inventors: Birama Goumballa, Cristian Pavao Moreira, Pierre Pascal Savary
  • Patent number: 10359451
    Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Yu-Ri Lim, Jong-Man Im
  • Patent number: 10355679
    Abstract: A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 16, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chien-Chuan Huang, Chia-Hsin Tung, Chun-Hung Chen, Hao-Jan Yang, Chieh-Hsiang Chang
  • Patent number: 10355688
    Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 16, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Cameron Brown, Yashodhan Vijay Moghe
  • Patent number: 10355699
    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Menno Spijker
  • Patent number: 10355671
    Abstract: Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a first passgate, a first latch, a second passgate, and a second latch. The first latch may include a first inverter and a first logic gate. The first logic gate may further include a second inverter and at least one voltage reducing component. The voltage reducing component may be an N-channel transistor or a P-channel transistor. Similarly, the second latch may include a third inverter and a second logic gate. The second logic gate may further include a fourth inverter and at least one voltage reducing component.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 16, 2019
    Assignee: LITTLE DRAGON IP HOLDING LLC
    Inventor: Mingming Mao
  • Patent number: 10355685
    Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 16, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Masahisa Iida, Masahiro Gion
  • Patent number: 10340732
    Abstract: According to one aspect, embodiments herein provide a UPS system comprising: a plurality of UPS's configured to be coupled in parallel, each UPS comprising: a bypass line selectively coupled between an input and an output via a bypass switch, wherein the bypass switch is configured to close in a first mode and to open in a second mode, and a controller coupled to the plurality of UPS's and configured to, in response to a determination that input power is at a desired level, control the bypass switch of a first UPS in the plurality of UPS's to operate in the first mode and provide a continuous output current waveform with an RMS value to the load, and selectively control the bypass switch of each other UPS to operate in the first mode such that an output current waveform provided by each UPS includes at least one delay period.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 2, 2019
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventor: Lars Nørup Bach
  • Patent number: 10340890
    Abstract: A high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 2, 2019
    Assignees: NUVOTON TECHNOLOGY CORP., NCKU RESEARCH & DEVELOPMENT FOUNDATION
    Inventors: Shuenn-Yuh Lee, Sz-An Chen
  • Patent number: 10320376
    Abstract: A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Richard Geiss
  • Patent number: 10313138
    Abstract: The invention relates to a powered device (2) like a luminaire for being used in a power distribution system (100), which is preferentially a PoE system and which comprises a power sourcing device (1) for sourcing a power to the powered device. The powered device comprises an electrical load like an LED and an electrical load power providing unit for generating from the sourced power an electrical load power and for providing the electrical load power to the electrical load, wherein the electrical load power providing unit is adapted to generate the electrical load power with a power level such that an input current drawn by the powered device from the power sourcing device is maximized below a predefined upper input current threshold. This allows increasing the power consumption of the powered device in comparison to the power consumption of powered devices in accordance with the PoE standard IEEE 802.3at.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: June 4, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Lennart Yseboodt, Matthias Wendt
  • Patent number: 10296024
    Abstract: A semiconductor switch control device includes a first FET and a second FET arranged adjacent to each other, in which source terminals are connected in series. A drain terminal of the first FET is connected to a high voltage battery, and a drain terminal of the second FET is connected to a high voltage load. A controller determines a temperature state of a minus-side main relay including the second FET based on a forward voltage of a body diode of the first FET.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: YAZAKI CORPORATION
    Inventors: Mitsuaki Morimoto, Eiichiro Oishi
  • Patent number: 10291179
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski