Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.

Abstract: An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.

Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .

Abstract: Methods, systems, and apparatus, including for back-up power sources. In one aspect, a method includes providing a plurality of first battery devices, each first battery device respectively electrically coupled to a respective server rack in a plurality of server racks and having a respective capacity to provide power to the respective rack for a power anomaly for up to a first duration. Providing a second battery device electrically coupled to the plurality of server racks and having a capacity to provide power to the plurality of respective server racks for a power anomaly for up to a second duration, wherein the second duration is longer than the first duration. A power anomaly is a deviation of mains power from one or more of a nominal supply voltage and frequency.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: Systems, methods, and devices are provided to efficiently share an antenna between multiple communication systems and allow for the communication systems to be simultaneously connected to the antenna with less attenuation and/or no fluctuation in signal strength. Communication circuitry may include an antenna that transmits and receives electromagnetic radiation. The communication circuitry may also include an antenna port that provides primary access to the antenna with a first attenuation via an antenna port input. Additionally, the communication circuitry may include a coupler attached to the antenna port. The coupler may provide secondary access to the antenna with a second attenuation.

Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Abstract: According to an embodiment of an electronic circuit, the electronic circuit includes a first input pin, a second input pin, an output pin, a control circuit and an output circuit. The first input pin is configured to receive a first input signal that includes an enable information and at least one operation parameter information. The second input pin is configured to receive a second input signal. The control circuit is configured to generate a drive signal based on the enable information included in the first input signal and the second input signal. The output circuit is configured to generate an output signal at the output pin such that a timing of the output signal is dependent on the drive signal and at least one parameter of the output signal is dependent on the at least one operation parameter information included in the first input signal.

Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.

Abstract: A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generates an oscillator signal including a constant frequency. The generator generates a generator signal including an initial frequency. The mixer is electrically coupled to the generator and the oscillator. The mixer combines the generator and oscillator signals to produce the microwave signal. The splitter is electrically coupled to the mixer. The splitter fans-out the microwave signal to a plurality of physical lines. Each of the plurality of physical lines is electrically connected to a corresponding one of the plurality of qubits.

Abstract: A charge pump circuit is provided, in which a charge pump is supplied with a temperature-dependent bias current, in particular a bias current that decreases with temperature.

Abstract: Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.

Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Abstract: A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.

Abstract: A current control system is disclosed. The current control system may include a controller configured to provide a control signal, an A/D converter dedicated to the controller, a driver configured to supply a current based on the control signal and a sensor configured to provide a digital signal representative of the current to the controller. The digital signal may bypass the dedicated A/D converter. A method for controlling current is likewise disclosed. A circuit for controlling current through an inductive load is likewise disclosed.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Abstract: The invention relates to a phase detection method (200) comprising the following steps: receiving (201) a receiving sequence (Yj) of values (Y0, Y1, . . . , YN?1) of a receiving signal (Y), said values (Y0, Y1, . . .

Abstract: A load management system is disclosed. The load management system may include a generator, a power source configured to drive the generator, a load bank configured to produce an electrical load on the generator, a chopper operatively connected to the generator and the load bank, and a chopper regulator in communication with the generator and the chopper. The chopper may be configured to modulate the electrical load of the load bank on the generator. The chopper regulator may be configured to monitor generator parameters and control the chopper based on the generator parameters.

Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.