Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: A power management system for dispensers is described. The system includes a controller connected to a lower power zero net voltage (ZNV) power source. A power rectification circuit (PRC) converts ZNV power to higher voltage direct current (HVDC) power. An energy storage system connected to the HVDC power source receives and stores HVDC power within the energy storage system which is selectively provided to a dispenser motor load connected to the energy storage system. The system provides an effective solution to the problem of transferring power from a low power battery source on a disposable product to a dispenser as well as providing a system that minimizes corrosion at the electrical interface between the disposable product and the dispenser particularly in higher humidity environments.

Abstract: The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.

Abstract: A drive circuit includes: a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and a capacitor having one end connected to a high side main terminal of the switching device, wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops.

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: A multi-stage charge pump including a first stage configured to generate a first output voltage, a last stage configured to receive the first output voltage from the first stage and output a second output voltage, a switch configured to receive the second output voltage from the last stage, and a voltage regulator circuit configured to control the second output voltage of the last stage to maintain a substantially constant on-resistance of the switch.

Abstract: A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.

Abstract: A drive circuit includes: a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and a capacitor having one end connected to a high side main terminal of the switching device, wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops.

Abstract: Device for adjusting the locking of an injection locked frequency multiplier, including: a first input receiving a first signal of frequency f1, and a second input receiving a second signal of frequency f2 outputted by the frequency multiplier; a sub-sampler of the second signal; a control circuit configured for: receiving a third signal corresponding to the second signal sub-sampled by the first signal or by another multiple signal of frequency of f1, then carrying out a high-pass or band-pass filtering of the third signal; determining that the frequency multiplier is locked on a multiple of f1 when the signal obtained after filtering is substantially zero, then outputting a signal the value of which is representative of the locking or not of the frequency multiplier.

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.

Abstract: A gate control circuit has a first gate controller that controls a gate voltage of a first transistor connected between a first reference voltage node and an output node on the basis of a potential difference between the first reference voltage node and a second reference voltage node, a second gate controller that controls a gate voltage of a second transistor connected between the output node and a fourth reference voltage node. and a voltage adjustment circuit that temporarily increases the potential difference between the first reference voltage node and the second reference voltage node in a first period in which the voltage of the first reference voltage node is rising from an initial voltage and a second period in which the voltage of the first reference voltage node is falling from a normal voltage.

Abstract: A semiconductor apparatus includes first and second edge detection signal generators. The first edge detection signal generator may generate a first edge detection signal by gating an input signal and its inverted signal based on a first gating control signal, generated by delaying the input signal, and output the first edge detection signal to an output node. The second edge detection signal generator may generate a second edge detection signal by gating a complementary signal of the input signal and its inverted signal based on a second gating control signal, generated by delaying the complementary signal, and output the second edge detection signal to the output node. An output signal may be generated at the output node.

Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

Abstract: An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0° phase component of an input signal and a 180° phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in ?phase(0°) based on the 0° the 180° phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90° phase component of the input signal and a 270° phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180°). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.

Abstract: A power management system for dispensers is described. The system includes a controller connected to a lower power zero net voltage (ZNV) power source. A power rectification circuit (PRC) converts ZNV power to higher voltage direct current (HVDC) power. An energy storage system connected to the HVDC power source receives and stores HVDC power within the energy storage system which is selectively provided to a dispenser motor load connected to the energy storage system. The system provides an effective solution to the problem of transferring power from a low power battery source on a disposable product to a dispenser as well as providing a system that minimizes corrosion at the electrical interface between the disposable product and the dispenser particularly in higher humidity environments.

Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.