Abstract: A debounce apparatus and a method thereof are provided, which includes a debounce module, a register and a timer. The debounce module receives an input signal and eliminates a bounce phenomenon of the input signal within a transient-time of the state-changing of the input signal to produce a debounce signal. The register outputs an output signal according to the value stored in the register. When the input signal changes its state, the timer starts time-counting according to a counting-value of settling-time; when the debounce signal changes its state, the timer recounts time; and when time-counting is ended and when the value corresponding to the debounce signal is different from the register's value, the register's value is updated by the value corresponding to the debounce signal. In this way, the apparatus can eliminate the system misjudgement problem caused by occurred voltage level errors in the stable state.

Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.

Abstract: A gate driving circuit includes a thermal sensing unit for sensing temperature to output a sensing voltage, a compare unit for comparing the sensing voltage with a reference voltage to output a control voltage, a charging control module for controlling a pre-charging operation according to the control voltage, and a plurality of shift register stages. Each shift register stage includes an input unit for outputting a driving control voltage according to a first input signal, a clock input unit for outputting a driving voltage according to a system clock, a driving unit for outputting a gate signal according to the driving control voltage and the driving voltage, and a pull-down unit for pulling down the gate signal and the driving control voltage according to a second input signal. The driving voltage is also controlled by the pre-charging operation for enhancing driving ability.