Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.

Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment, an output driver and a bias voltage controller are included. The bias voltage controller is coupled to provide first and second bias voltages to the output driver. The bias voltage controller comprises a bias generator coupled to a first voltage supply, a second voltage supply, and a ground node. The bias generator has a first bias node for sourcing the first bias voltage. The first voltage supply is configured to provide a higher voltage level than the second voltage supply. A resistor-divider network is coupled to the first voltage supply and the ground node. A watch dog circuit is coupled to the resistor-divider network, bias generator, and the ground node. A comparison circuit is coupled to the bias generator and the second voltage supply. The comparison circuit has a second bias node for sourcing the second bias voltage.

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.

Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.

Abstract: An electronic switching device comprises a first bipolar junction transistor (BJT) (2a) adapted to control the flow of current between a pair of switching terminals; a charge recovery circuit coupled to the base of the first BJT (2a) and adapted to establish a supply voltage across a capacitor (5) by storing in the capacitor (5) charge carriers accumulated in the base of the first BJT (2a) during application of a base drive current, the quantity of accumulated charge carriers depending on the base drive current; and a controllable current source (4) adapted to control the base drive current, thereby controlling the supply voltage.

Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

Abstract: Voltage controlled variable attenuators are described that are configured to be coupled to a transmission path to furnish variable attenuation of a signal, such as a radio frequency signal. In one or more implementations, the voltage controlled variable attenuator includes at least one transistor. The transistor has an open configuration for at least substantially preventing the flow of current through the transistor, and a closed configuration for at least partially allowing the flow of current through the transistor. The variable attenuator also includes a resistive component coupled to the transistor, and configured to couple to the transmission path. The resistive component is configured to at least partially mitigate non-linear effect when the transistor transitions from the open configuration to the closed configuration.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.

Abstract: A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.

Abstract: A phase detector, which forms a semiconductor device, detects a phase difference between a reference signal and a feedback signal obtained by feeding back an output signal of an oscillator, and generates a phase difference value indicating a value in accordance with the phase difference. An amplifier amplifies the phase difference value at a gain determined in accordance with a control signal from outside the device. A filter smoothes an output value of the amplifier. The oscillator controls a frequency of the output signal in accordance with an output value of the filter.

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract: An inter-line switching element formed of a MOSFET is provided between a pair of signal lines. When the level of a differential signal changes from high to low, a control circuit turns on the FET for a fixed period thereby to suppress ringing by decreasing the impedance between the signal lines when the level of the differential signal transitions, and causing the energy of the distortion of the differential signal waveform to be absorbed by the on-resistance of the FET.