Abstract: A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.

Abstract: A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages.

Abstract: A protective device for a voltage-controlled semiconductor switch has a gate connection, a power emitter connection, an auxiliary emitter connection and a collector connection. The semiconductor switch can switch a current between the collector connection and the power emitter connection. A voltage-limiting device limits the voltage between the gate connection and the power emitter connection. A deactivation device is connected to the voltage-limiting device and deactivates the voltage-limiting device during a switch-on of the semiconductor switch.

Abstract: A device of triggering and generating temperature coefficient current for generating a temperature coefficient current includes a positive temperature coefficient current generating unit, for generating a first positive temperature coefficient current, a negative temperature coefficient current generating unit, for generating a first negative temperature coefficient current, and a triggering unit, for triggering to generate the temperature coefficient current according to a triggering temperature and a current difference between the first positive temperature coefficient current and the first negative temperature coefficient current.

Abstract: An apparatus comprising a switch, a balun and a splitter. The switch may be configured to provide (i) a first signal on a first path when a power signal is not present and (ii) a second signal on a second path when the power signal is present. The first path activates only the first signal. The second path activates only the second signal. The balun circuit may be configured to convert the second signal to a differential signal. The splitter circuit may be configured to generate a plurality of differential output signals in response to the differential signal.

Abstract: A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.

Abstract: A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.

Abstract: In one aspect, a duty cycle controller includes a first port configured to receive a voltage bias signal, a second port configured to receive an input voltage signal, a third port configured to provide an output signal of the duty cycle controller having a duty cycle and a n-bit digital-to-analog converter (DAC) configured to receive the voltage bias signal and to provide a DAC output signal to a comparator. The DAC output signal has a peak value. The duty cycle controller also includes the comparator configured to compare the DAC output signal from the n-bit DAC with the input voltage signal to provide a comparator output signal. The comparator output signal is used to provide the output signal of the duty cycle controller and the duty cycle changes with changes to the input voltage signal.

Abstract: Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations.

Abstract: A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.

Abstract: A luminaire provides light having a distribution pattern with high center beam candle power and a gradual gradient across a wide area. The luminaire includes a light source having first and second sets of light emitting elements selected and positioned to achieve the desired light distribution pattern. The luminaire further includes an optic configured to refract light emitted from the light source to achieve the desired light distribution pattern.

Abstract: An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current signals from a plurality of signal sources are output to the output line. The current mirror circuit is electrically connected to the output line. The comparator is configured to compare a mirrored current signal from the current mirror circuit with a reference current signal. The comparator is configured to output a signal representing a comparison result of amplitudes of the mirrored current signal and the reference current signal.

Abstract: According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the control electrode is electrically separated from a source electrode, a drain electrode, and a gate electrode of the power device. The control voltage is separately applied to the control electrode. The method may include applying a negative control voltage to the control electrode prior to applying a gate voltage to the gate electrode.

Abstract: A multiplex circuit includes a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points; a plurality of common base transistors, each common base transistor corresponding to a respective input transistor and having an emitter that is connected in series to a collector of the respective input transistor; and an output end that is connected to a collector of each of the common base transistors, and to which a signal that is obtained by combining signals output by each of the input transistors based on the plurality of input signals.

Abstract: The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period.

Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Abstract: Embodiments of the invention are generally directed to a configurable single-ended driver. An embodiment of an apparatus includes an interface with a channel; and a single-ended driver to drive a signal on the channel, wherein the driver includes a mechanism to configure a termination resistance of the driver, configure a voltage swing of the driver, and configure a signal response of the driver.

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.